AD74115 datasheet(97/103 Pages) AD

97 / 103 page

Data Sheet

AD74115

analog.com

Rev. 0 | 97 of 103

Table 66. Bit Descriptions for ALERT_MASK

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

ANALOG_IO_OC_MASK

Mask Bit for ANALOG_IO_OC.

0x0

R/W

ANALOG_IO_SC_MASK

Mask Bit for ANALOG_IO_SC.

0x0

R/W

DO_INT_TIMEOUT_MASK

Mask Bit for DO_INT_TIMEOUT.

0x0

R/W

DO_EXT_TIMEOUT_MASK

Mask Bit for DO_EXT_TIMEOUT.

0x0

R/W

DO_INT_SC_MASK

Mask Bit for DO_INT_SC.

0x0

R/W

DO_EXT_SC_MASK

Mask Bit for DO_EXT_SC.

0x0

R/W

DO_THERM_RESET_MASK

Mask Bit for DO_THERM_RESET.

0x0

R/W

DI_OC_ERR_MASK

Mask Bit for DI_OC_ERR.

0x0

R/W

DI_SC_ERR_MASK

Mask Bit for DI_SC_ERR.

0x0

R/W

ADC_ERR_MASK

Mask Bit for ADC_ERR.

0x0

R/W

TEMP_ALERT_MASK

Mask Bit for TEMP_ALERT.

0x0

R/W

PPC_ERR_MASK

Mask Bit for PPC_ERR.

0x0

R/W

SPI_ERR_MASK

Mask Bit for SPI_ERR.

0x0

R/W

[1:0]

RESERVED

Reserved.

0x0

Alert Mask Register for SUPPLY_ALERT_STATUS

Address: 0x60, Reset: 0x0000, Name: SUPPLY_ALERT_MASK

This register is used to mask specific SUPPLY_ALERT_STATUS bits from activating the ALERT pin. The position of mask bits in this register

line up the corresponding status bits in the SUPPLY_ALERT_STATUS register. To mask a particular alert, set the corresponding mask bit to 1.

Note that masking a bit does not prevent it from setting the equivalent alert bit in the ALERT_STATUS register.

Mask Bit for AVDD_ERR.

Mask Bit for CAL_MEM_ERR.

Mask Bit for the AVSS_ERR.

Mask Bit for DO_VDD_ERR.

Mask Bit for the DVCC_ERR.

Mask Bit for ALDO1V8_ERR.

Mask Bit for AVCC_ERR.

[15:7] RESERVED

[0] AVDD_ERR_MASK (R/W)

[6] CAL_MEM_ERR_MASK (R/W)

[1] AVSS_ERR_MASK (R/W)

[5] DO_VDD_ERR_MASK (R/W)

[2] DVCC_ERR_MASK (R/W)

[4] ALDO1V8_ERR_MASK (R/W)

[3] AVCC_ERR_MASK (R/W)

Table 67. Bit Descriptions for SUPPLY_ALERT_MASK

Bits

Bit Name

Description

Reset

Access

[15:7]

RESERVED

Reserved.

0x0

CAL_MEM_ERR_MASK

Mask Bit for CAL_MEM_ERR.

0x0

R/W

DO_VDD_ERR_MASK

Mask Bit for DO_VDD_ERR.

0x0

R/W

ALDO1V8_ERR_MASK

Mask Bit for ALDO1V8_ERR.

0x0

R/W

AVCC_ERR_MASK

Mask Bit for AVCC_ERR.

0x0

R/W

DVCC_ERR_MASK

Mask Bit for the DVCC_ERR.

0x0

R/W

AVSS_ERR_MASK

Mask Bit for the AVSS_ERR.

0x0

R/W

AVDD_ERR_MASK

Mask Bit for AVDD_ERR.

0x0

R/W

Readback Select Register

Address: 0x64, Reset: 0x0000, Name: READ_SELECT

This register selects the address of the register required to be read back and determines the contents of the SPI readback frame.

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