AD74115 datasheet(3/103 Pages) AD

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Data Sheet

AD74115

SPECIFICATIONS

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Rev. 0 | 3 of 103

VOLTAGE OUTPUT

AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5 V

to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. The sense resistor (RSENSE) = 100 Ω (ideal), the load

resistor (RLOAD) = 100 kΩ, and the load capacitor (CLOAD) = 4.7 nF per the recommended configuration. Note that the headroom specification

for AVDD and AVSS must be considered when setting supply voltages.

Table 1. Voltage Output

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE OUTPUT

Resolution

Bits

Output Range

−12

+12

ACCURACY

Total Unadjusted Error (TUE)

−0.2

+0.2

%FSR

TUE at 25°C

−0.1

+0.1

%FSR

Integral Nonlinearity (INL)

−3.0

+3.0

LSB

Differential Nonlinearity (DNL)

−1.0

+1.0

LSB

Guaranteed monotonic

Offset Error

−5.5

+5.5

Error with Code 0x0000 loaded to the DAC, 0 V to 12 V range only

Offset Error at 25°C

−3.0

+3.0

0 V to 12 V range only

Bipolar Zero Error

−13

+13

Error with midscale code loaded to the DAC in a ±12 V range

Bipolar Zero Error at 25°C

−13

+13

±12 V range only

Gain Error

−0.2

+0.2

%FSR

Gain Error 25°C

−0.12

+0.12

%FSR

OUTPUT CHARACTERISTICS

Load1

100

kΩ

Headroom1

2.2

Voltage difference required between AVDD and the input and output

positive (I/OP) screw terminal to provide 12 V across a 1 kΩ load

Footroom1

2.2

Voltage difference required between AVSS and the I/OP screw

terminal to provide −12 V across a 1 kΩ load

Short-Circuit Current

Sourcing and sinking, I_LIMIT bit = 0 (default)

Sourcing and sinking, I_LIMIT bit = 1

Short-Circuit Activation Time1

Time in short circuit before alert is generated

Maximum Capacitive Load1

Maximum system capacitance on the I/OP screw terminal, including

the recommended 4.7 nF CLOAD when the compensation capacitor

(CCOMP) is not connected

µF

Maximum system capacitance on the I/OP screw terminal, including

the recommended 4.7 nF CLOAD when a CCOMP = 220 pF is connected

DC Output Impedance1

0.1

Ω

DC Power Supply Rejection Ratio (PSRR)1

PSRR measured with a change in AVDD

DYNAMIC PERFORMANCE1

Output Voltage (VOUT) Settling Time

µs

11 V step (0.5 V to 11.5 V or 11.5 V to 0.5 V) to ±0.05 % FSR, CLOAD =

4.7 nF, and no CCOMP is connected

110

µs

22 V step (−11 V to +11 V or +11 V to −11 V) to ±0.05 % FSR, CLOAD =

4.7 nF, and no CCOMP is connected

Output Voltage Settling Time with CCOMP

Connected

400

µs

11 V step (0.5 V to 11.5 V or 11.5 V to 0.5 V) to ±0.05 % FSR, CLOAD =

4.7 nF, and 220 pF CCOMP is connected

400

μs

22 V step (−11 V to +11 V or +11 V to −11 V) to ±0.05 % FSR, CLOAD =

4.7 nF, and 220 pF CCOMP is connected

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