AD74115 datasheet(11/103 Pages) AD

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Data Sheet

AD74115

SPECIFICATIONS

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Rev. 0 | 11 of 103

DIGITAL OUTPUTS (SOURCING AND SINKING)

DO_VDD = +10 V to +35 V, AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7

V to +5.5 V, AVCC = +4.5 V to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. CLOAD = 4.7 nF per the

recommended configuration.

Table 11. Digital Outputs (Sourcing and Sinking)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DO_VDD SUPPLY RANGE

EXTERNAL DIGITAL OUTPUT

Sourcing and sinking

Short Circuit

Short-Circuit Voltage, VSC1

160

240

With a 0.15 Ω set resistor (RSET), the current clamps at 1.3 A

Short-Circuit Voltage, VSC2

120

With a 0.15 Ω RSET, the current clamps at 667 mA

Short-Circuit Clamp Time1

1.2

µs

FET input capacitance (CISS) < 500 pF, and the time for the

short-circuit clamp to engage during a 0 Ω short-circuit

Time Out 1, T11

0.1

100

Typical programmable times

Time Out 2, T21

0.1

Typical programmable times

On and Off Times1

On Time, tON

µs

FET CISS < 500 pF, and the time from SYNC rising edge to settle

to 90%

Off Time, tOFF

µs

FET CISS < 500 pF, and the time from the SYNC rising edge to

FET disable

Gate Drive Voltage

Current Sourcing

−12

−10

−8

The DO_SRC_GATE voltage with respect to DO_VDD

Current Sinking

AVCC

The DO_SNK_GATE voltage

DO_SRC_DGATE Current Sink

To AVSS, when DO_EXT_MODE is configured for the external

source with a smart diode

INTERNAL DIGITAL OUTPUT

On Resistance, RON

Sourcing Mode

Ω

Sinking Mode

3.5

Ω

Short-Circuit

Short-Circuit Current 1

220

350

Short-Circuit Current 2

105

180

Short-Circuit Clamp Time1

µs

Time for the short-circuit clamp to engage during a 0 Ω short

circuit

Time Out 1, T11

0.018

100

Typical programmable times

Time Out 2, T21

0.018

Typical programmable times

Thermal Shutdown1

Thermal shutdown for internal digital output

Disabled Temperature

140

°C

Reenabled Temperature

130

°C

On and Off Times1

On Time, tON

μs

Time from the SYNC rising edge to settle to 90%

Off Time, tOFF

μs

Time from the SYNC rising edge to FET disable

PUSH AND PULL MODE1

Push and pull timing for the external FET is dependent on the

CISS of the external FET

Output Data Rate

Internal FETs

kHz

External FETs

kHz

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