AX88780 datasheet(11/49 Pages) ASIX

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AX88780

2.7 Miscellaneous

Table 6 : Miscellaneous signals group

Pin Name

Type

Pin No.

Pin Description

LINKLED

IO,

12mA,

In power-on reset phase, this pin will be latched by AX88780 to determine that system

operates in 32 or 16-bit mode. High state is 16-bit mode and low state is 32-bit mode.

The default is in 32-bit mode.

Upon finishing reset status, if bit11 of PHY_CTRL register is enabled, this pin stands

for:

Link: indicates a good link status, active low in 16-bit mode and active high in 32-bit

mode.

Traffic: indicates the traffic status and flashes while in TX or RX state.

If bit11 of PHY_CTRL is not enabled, this pin is as general-purpose pin and

controlled by GPIO_CTRL register.

SPDLED

IO,

12mA,

In power-on reset phase, this pin will be latched by AX88780 to determine whether

AX88780 swaps the data or not. If the high state, AX88780 will sap the data. The

default is little-endian.

Upon finishing reset stage, if bit12 PHY_CTRL register is enabled, this pin stands for

speed mode. Low indicates PHY is in 10BASE-TX mode, and high state indicates

PHY in 100BASE-T mode.

This pin is tied to ground for normal operation.

TEST0

I3, PD

Floating for normal operation.

TEST1

I3, PD

Floating for normal operation.

XTLN

25MHz Crystal clock output.

XTLP

25MHz Crystal clock input. (Note:

±50ppm, max. 33pF load capacitance)

RSTPB

Power-up reset signal. Active low. This pin must be connected with RST_N pin.

IBREF_WESD I

Connect a 12.3Kohm resistor to ground.

67,68

No connection

2.8 Power/ground pin

Table 7 : Power/Ground pins group

Pin Name

Type

Pin No.

Pin Description

VCC33

VCC3

1,13,40, 105, 119

Digital 3.3V power

VCC25

VCC2

4,20,27,35,57,60,64,72,78,107,117,123

Digital 2.5V power

GND

8, 56, 73,106

Digital ground

VCC25A

VCC2A 81,85,89,96,98,100

2.5V power for PHY analog part

GNDA

GNDA 82,86,87,92,95,99,101

Analog ground

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