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AX88780 Datasheet(PDF) 26 Page - ASIX Electronics Corporation |
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AX88780 Datasheet(HTML) 26 Page - ASIX Electronics Corporation |
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26 / 49 page  AX88780 0 = disable (default) 3:2 - R/W 2’b00 Reserved 1 SRST_PHY R/W 1 Software Reset Internal PHY Driver set this bit to ‘0’ to reset internal PHY. The reset duration is depended on whenever this bit is de-asserted by deriver. 1 = in normal operation 0 = in reset status 0 SRST_MAC R/W 1 Software Reset MAC Driver set this bit to ‘0’ to reset MAC. The reset duration is depended on whenever this bit is de-asserted by deriver. 1 = in normal operation 0 = in reset status 4.24 MACID0--MAC ID0 Register Offset Address = FC70h Default = 32’h0000_0000 Field Name Type Default Description 31:16 - R All 0’s Reserved. 15:0 MID15_0 R/W 16’h0000 MAC ID Address [15:0]. This field defines lower address bit15 to bit0 of MAC. The MACID0, MACID1 and MACID2 combine into 48-bit MAC address. The MAC address format is [47:0] = {MACID2[15:0], MACID1[15:0], MACID0[15:0]}. If the EEPROM is attached, this field will be auto-loaded from EEPROM after hardware reset. 4.25 MACID1--MAC ID1 Register Offset Address = FC74h Default = 32’h0000_0000 Field Name Type Default Description 31:16 - R All 0’s Reserved. 15:0 MID31_16 R/W 16’h0000 MAC ID Address [31:16]. 4.26 MACID2--MAC ID2 Register Offset Address = FC78h Default = 32’h0000_0000 Field Name Type Default Description 31:16 - R All 0’s Reserved. 15:0 MID47_32 R/W 16’h0000 MAC ID Address [47:32]. 4.27 TXLEN--TX Length Register Offset Address = FC7Ch Default = 32’h0000_05FC Field Name Type Default Description 31:11 - R All 0’s Reserved 10:0 MAXTXLEN R/W 11’h5FC Max TX packet size This field defines the maximum raw packet size in transmittance. It is not included 4 bytes FCS. 26 ASIX ELECTRONICS CORPORATION |
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