AX88780 datasheet(33/49 Pages) ASIX

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AX88780

5.0 PHY Register

AX88780 is built a high performance 10/100M PHY for cost-effective. Driver can access these registers of PHY by

in-directed mechanism. For write operation, software firstly sets data to MDIODP register, then sets index and write enable

bit to MDIOCTRL register. AX88780 will access PHY by internal interface and clear the write enable bit whenever the

operation finished. For read operation, driver sets the index and read enable bit to MDIOCTRL register, then polls the

read-enable bit. The returned data will be put in MDIODP register whenever the read-enable bit is cleared.

Table 9 : PHY Register Mapping

Index

Name

Description

00h

BMCR

Basic Mode Control Register

01h

BMSR

Basic Mode Status Register

02h

PHYIDR0

PHY Identifier 0 Register

03h

PHYIDR1

PHY Identifier 1 Register

04h

ANAR

Auto-negotiation Advertisement Register

05h

ANLPAR

Auto-negotiation Link Partner Ability Register

06h

ANER

Auto-negotiation Expansion Register

The following abbreviations apply to below sections for detained register description.

Access type

R = read only

RW= read/write

Attribute:

LL = latch low

LH = latch high

SC = Self-clearing

PS = Value is permanently set

X = don’t care

5.1 BMCR--Basic Mode Control Register

Index = 00h

Field

Name

Type

Default

Description

PHYRST

R/W

0, SC

Soft reset:

1 = software reset PHY, this bit will be cleared when reset finish.

0 = normal operation

LOOPBACK

R/W

Loop back operation:

1 = Loop back enable

0 = Loop back disable

SPDSEL

R/W

Speed selection:

1 = 100Mb/s

0 = 10Mb/s

AUTONEG_EN RW

Auto-negotiation enable:

1 = enable, bit8 and bit13 will be ignored when this bit is enabled.

0 = disable, bit8 and bit13 of this register determine the link speed and

mode.

PHYPWDN

R/W

Power down:

1 = power-down enable

0 = normal operation

Reserved

AUTONEG_RS R/W

Auto-negotiation restart:

1=Restart auto-negotiation, this bit will be cleared when finish

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