AX88780 datasheet(28/49 Pages) ASIX

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AX88780

7:5

3’b000

Reserved

4:0

PHYID

R/W

5’b00000 PHY ID

If driver wants to access PHY, set this field to define the address (ID) of PHY.

The address of internal PHY is fixed to 10h

4.30 MDIODP--MDIO Data Port Register

Offset Address = FC88h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

MDPORT R/W

All 0’s

PHY Data Port

To or from internal PHY data is put in this field.

4.31 GPIO_CTRL--GPIO Control Register

Offset Address = FC8Ch

Default = 32’h0000_0003

Field

Name

Type

Default

Description

31:10

All 0’s

Reserved

GPIO1S

R/W

GPIO1 Status

This bit stands for the pin status of GPIO1 when it is set to input mode.

1 = high state

0 = low state

GPIO0S

R/W

GPIO0 Status

This bit stands for the pin status of GPIO0 when it is set to input mode.

1 = high state

0 = low state

7:2

All 0’s

Reserved

GPIO1DIR R/W

GPIO1 Mode Direction

This field defines the direction of GPIO1 pin.

1 = input mode

0 = output mode

GPIO0DIR R/W

GPIO0 Mode Direction

This field defines the direction of GPIO pin.

1 = input mode

0 = output mode

Note: For output mode, software must set the bit0 or bit1 to output mode then set bit8 or bit9.

4.32 RXINDICATOR--Receive Indicator Register

Offset Address= FC90h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:1

All 0’s

Reserved

RXSTART R/W

Receive Start

Driver set this bit to start or end receive operation from RX buffer of MAC.

1= Start read RX buffer

0= End read RX buffer

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