AX88780 datasheet(13/49 Pages) ASIX

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AX88780

3.5 Flow Control

In full duplex mode, AX88780 supports the standard flow control mechanism defined in IEEE 802.3x standard. It

enables the stopping of remote node transmissions via a PAUSE frame information interaction. When space of the packet

buffer is less than the threshold values (RXBTHD0, RXBTHD1), AX88780 will send out a PAUSE-ON packet to stop the

remote node transmission. And then AX88780 will send out a PAUSE-OFF packet to inform the remote node to retransmit

packet if it has enough space to receive packets.

3.6 Checksum Offloads and Wake-up

To reduce the computing loading of CPU, AX88780 is built checksum operator for IP, UDP or TCP packet. AX88780

will detect the packet whether it is IP, UDP or TCP packet. If it is an IP packet, AX88780 will calculate the checksum of

header and put the result in checksum filed of IP. Then it continuously checks the packet whether it is UDP or TCP. It will

perform the checksum operation whenever it is a UDP or TCP packet. AX88780 also automatically skip the VLAN tag

when checksum is executed. AX88780 also supports to detect magic packet or link-up to wake up system when system is in

sleep state.

3.7 Fast-Mode support

To improve the throughput in embedded system, AX88780 supports fast-mode for TX/RX buffer access. Host can

access AX88780 by driving CSN to low and toggle WEN (write) or OEN (read). AX88780 can support the burst until

whole packet access. The access timing can refer to section 6.2.4 and 6.2.6. This mechanism is only for TX/RX buffer

access. For configuration register access, it must use single-burst.

3.8 Big/Little-endian support

AX88780 supports “Big” or “Little” endian data format. The default is Little-endian. Designer can pull-up SPDLED

pin to high to swap the data format. Below table can depict the relation. This swap is only valid in 32-bit mode.

L ittle-en d ian

D [31:24]

D [23:1 6]

D [15 :8 ]

D [7 :0 ]

D [7:0]

D [1 5 :0 ]

D [2 3:16 ]

D [3 1 :24 ]

B ig-end ian

Figure 4 : data swap block

3.9 10/100BASE-TX PHY

AX88780 integrates high performance PHY that is fully compliant with 10/100BASE-TX Ethernet standards such as

IEEE 802.3, IEEE 802.3u and ANSI X3.263-1995. It’s main features can described below.

Adaptive equalizer

This equalizer mainly eliminates the distortions caused by inter-symbol interference (ISI) by automatically adjusting

the mathematical coefficient to match the cable length.

Baseline wander correct

The transmitter sends DC and AC signals as a pair. The receiving device and transmitting device each have a

transformer that blocks the Dc signal. When the AC signal loses its DC component, the AC signal becomes distorted. The

Baseline-Wander correct ill restores the DC component to AC signal and delivers it as a complete signal to receiver.

Link monitor/signal detect

This feature is used to detect the signal’s level. If the detected signal is above 400mV in 100BASE-TX mode, it will

generate a Signal Detected (SD) to MAC. If the level is below 400mV, the SD signal will be de-asserted 1ms.

Carrier detect and 4B/5B coding

The Physical Coding Sub-layer (PCS) checks with Physical Medium Attachment (PMA) data to see if the packets

meet IEEE 802.3u defined preamble (J/K/packets in 100BASE-TX) standards. If the packets meet the standards, the PCS

sub-layer will start to process the data and send to MAC engine. The PCS converts received/transmitted data according

IEEE 802.3u defined coding standards, such as 4B/5B and scrambling/de-scrambling.

ASIX ELECTRONICS CORPORATION

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