AX88780 datasheet(23/49 Pages) ASIX

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AX88780

4.14 RXBOUND--RX Boundary Pointer Register

Offset Address = FC38h

Default = 32’h0000_07FF

Field

Name

Type

Default

Description

31:11

All 0’s

Reserved

10:0

RXBUNPTR

R/W

All 0’s

RX Line Boundary Pointer.

Point to the last line that has been read by driver. The unit of line is 16

bytes.

When driver finished reading packet from RX buffer, it must update this

field.

4.15 MAC_CFG0--MAC Configuration0 Register

Offset Address = FC40h

Default = 32’h0000_9157

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

SPEED100

R/W

Line Speed Mode

When this bit is enabled, The MAC of AX88780 will operate in 100M

speed, otherwise it will operate in 10M speed. The line speed must

co-operate with setting of PHY.

1 = 100M

0 = 10M

R/W

Reserved, this bit must set to 0 for normal operation

R/W

Reserved, this bit must set to 0 for normal operation.

TXFLOW_EN

R/W

TX Flow Control

If this bit is enabled, MAC will perform TX flow control and send pause

on/off frame when receive buffer become low water level.

1 = enable

0 = disable

R/W

Reserved, this bit must set to 0 for normal operation.

10:4

IPGT

R/W

7’h15

Inter Packet Gap time: (IPG)

This field defines the back-to-back transmit packet gap for 10.100M only.

3:0

R/W

4’h7

Reserved, keep the default value for normal operation.

4.16 MAC_CFG1--MAC Configuration1 Register

Offset Address = FC44h

Default = 32’h0000_6000

Field

Name

Type

Default

Description

31:15

All 0’s

Reserved

PUSRULE

R/W

Pause Frame Check Rule

When this bit is set, AX88780 accepts pause frame that DA can be any

value.

1 = don’t check DA field.

0 = check DA is equal to “01 80 C2 00 00 01”

CRCCHK

R/W

Check CRC of received Packet.

When this bit is enabled, AX88780 will drop any CRC error packet.

1 = enable

0 = disable

12:7

R/W

All 0’s

Reserved, keep all bits in ‘0’ for normal operation.

DUPLEX

R/W

Duplex Mode.

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