AX88780 datasheet(8/49 Pages) ASIX

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AX88780

2.0 Signal Description

2.1 Signal Type Definition

I3:

Input, 3.3V with 5V tolerance

I2:

Input, 2.5V with 3.3V tolerance

O3:

Output, 3.3V

O2:

Output, 2.5V

IO3:

Input/Output, input 3.3V with 5V tolerance

TSO:

Tri-State Output

OD:

Open Drain allows multiple devices to share as a wire-OR

PD:

Internal 75K Pull Down

PU:

Internal 75K Pull Up

GND:

Digital Ground

GNDA:

Analog Ground

GNDR:

Ground for Regulator

VCC3:

3.3V power

VCC3R:

3.3V for regulator

VCC2:

2.5V power

VCC2A:

2.5V for analog

Input only

Output only

IO:

Input/Output

2.2 Host Interface

Table 1 : Host Interface signals group

Pin Name

Type

Pin NO

Pin Description

INTN

TSO, 8mA

102

Interrupt to host system

When the polarity is active high, this signal must be pulled low, otherwise pulled

high in active low environment. Software set the bit6 of command register (CMD) to

response the polarity.

RST_N

103

Reset signal: active low.

HCLK

104

System Clock. The reference frequency is from 40MHz to 100MHz

WAKEUP

TSO, 8mA

115

Wake-up signal to system. When the polarity is active high, this signal must be

pulled low, otherwise pulled high in active low environment. Software set the bit0 of

command register (CMD) to response the polarity.

HD0

IO3, 8mA

Data bus bit0.

HD1

IO3, 8mA

Data bus bit1.

HD2

IO3, 8mA

Data bus bit2.

HD3

IO3, 8mA

Data bus bit3.

HD4

IO3, 8mA

Data bus bit4.

HD5

IO3, 8mA

Data bus bit5.

HD6

IO3, 8mA

Data bus bit6.

HD7

IO3, 8mA

Data bus bit7.

HD8

IO3, 8mA

Data bus bit8.

HD9

IO3, 8mA

Data bus bit9.

HD10

IO3, 8mA

Data bus bit10.

HD11

IO3, 8mA

Data bus bit11.

HD12

IO3, 8mA

Data bus bit12.

HD13

IO3, 8mA

Data bus bit13.

HD14

IO3, 8mA

Data bus bit14.

HD15

IO3, 8mA

128

Data bus bit15.

HD16

IO3, 8mA

127

Data bus bit16, internal pull low.

ASIX ELECTRONICS CORPORATION

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