INDT331B datasheet(12/40 Pages) ETC1

12 / 40 page

Preliminary Data Sheet

INDT/R166B

INDT/R331B

Date: 2005-03-14 Revision: 0.1

Page 12 of 40

2 Device Configuration

The GigaSTaR Digital Display Link allows for configuring the pixel-, sideband- and audio-interface.

2.1 Pixel Clock Conditioning (Rx only)

In order to allow for interfacing with devices being susceptible to any clock variations the Rx device provides the capability

to compensate for that.

PX_CLK_OUT holds the pixel clock signal as it has been created from the embedded clock in the data stream. Those

signals are typically afflicted with jitter, which may cause invalid data on interfacing devices dependent on its PLL

performance. By feeding back the PX_CLK_OUT via an external PLL into the PX_CLK_IN, the PX_CLK signal can be de-

jittered. As soon the PX_CLK_IN receives a valid frequency of 20MHz or higher the pixel data outputs are enabled and the

PX_CLK provides the valid and jitter-free pixel clock accordingly.

INDR

Receiver

PX_CLK_IN

PX_CLK_OUT

PX_CLK

PX_D0…47

PLL

Figure 2.1: Pixel Clock conditioning

When PX_CLK_IN is tied to logic HIGH the pixel data outputs PX_D0…D47 are tri-stated.

When PX_CLK_IN is tied to logic LOW the Rx166/Rx331 operates as Rx165/Rx330, with the restriction that the PX_CLK-

(signal provided by Rx165/Rx330) is not available. In this case the PX_CLK holds the pixel clock signal as it has been

created from the embedded clock in the data stream. Though the 166/331series can be used in applications designed for

165/330-series, other combinations than pairs (Tx and Rx) of the same series are not compatible.

Note: The external PLL shall have an integrating characteristic to prepare the PX_CLK signal for proper and stable

interfacing with devices (DVI/LVDS) whose internal PLL performance may cause data loss especially at higher frequencies

and resolutions.

INDT331B Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers