14 / 40 page
Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 14 of 40
BUF
EN1
EN2
4
4
BUF
EN1
EN2
4
4
BUF
EN1
EN2
4
4
cfg2
0
1
2
3
CFG_CYC
CFG_SEL[3:0]
(SB0_D[3:0])
INDT
SB0
SB2
CFG_D[3:0]
(SB2_D[3:0])
cfg0
cfg1
BUF
EN1
EN2
44
BUF
EN1
EN2
44
BUF
EN1
EN2
44
BUF
EN1
EN2
44
0
1
2
3
CFG_CYC
CFG_SEL[3:0]
(SB2_D[3:0])
INDR
CFG_D[3:0]
(SB0_D[3:0])
cfg0
SB2
SB0
cfg1
cfg2
cfg3
0
1
2
0
1
2
3
Figure 2.2: Configuration Logic
Each configuration vector’s default setting is “1111”. This popular operating mode (see light gray lines on following tables)
can easily be established with pull-up resistors from the configuration inputs to VCC instead of tri-state buffers. All
configuration vectors are valid for transmitter and receiver, unless otherwise noted.
2.3 Configuration Process and Timing
Figure 2.3 shows the configuration process.
RESET#
CFG_CYC
CFG_SEL[3:0]
CFG_D[3:0]
Internal clock
registers
config data
0x1
0x2
0x4
cfg0
cfg1
cfg2
cfg3
0x0
0x0
0x0
0x0
0x8
0x0
Figure 2.3: Timing of Configuration Process
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