Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 30 of 40
4.3 INDT331B Transmitter Signal Description
Pin Name
Pin
Dir
Type
Description
Link Interface
TX0+
B12
OUT
CML
TX0–
B13
OUT
CML
Serial Data Output (Downlink 0)
TX1+
B5
OUT
CML
TX1–
B6
OUT
CML
Serial Data Output (Downlink 1)
RX2+
A10
IN
CML
RX2–
A9
IN
CML
Serial Data Input (Uplink)
LOCK0
B10
OUT
LVTTL
Lock Indicator 0. HIGH when PLL of Downlink 0 is properly locked
LOCK1
B3
OUT
LVTTL
Lock Indicator 1. HIGH when PLL of Downlink 1 is properly locked
SYNC2
C2
OUT
LVTTL
HIGH when the Uplink is frame synchronous
Pixel Interface
PX_CLK+
T18
IN
LVTTL*
Pixel clock 24 – 161 MHz, diff + or single-ended
PX_CLK–
R18
IN
LVTTL*
Pixel clock 24 – 161 MHz, diff – pull to GND in single ended mode
PX_D[47:0]
(see Table
4.9)
IN
LVTTL*
Configurable parallel pixel data interface
PX_HSYNC
R17
IN
LVTTL*
Pixel data framing – Horizontal sync pulse (active HIGH)
PX_VSYNC
P18
IN
LVTTL*
Pixel data framing – Vertical sync pulse (active HIGH)
PX_DE
P17
IN
LVTTL*
Pixel data framing – Data enable (active HIGH)
VREF
N18
IN
A
Configures the input level of the pixel interface
Sideband Interface
SB0_CLK
C18
OUT
LVTTL
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB0_D[3:0]
(CFG_SEL[3:0])
A16,A17,A
18,B18
OUT
LVTTL
If CFG_CYC=0: Sideband Data Channel 0 Upstream Output
If CFG_CYC=1: Configuration vector output
SB1_CLK
G18
OUT
LVTTL
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB1_ D[1:0]
F18,F17
OUT
LVTTL
Sideband Data Channel 1 Upstream Output
SB2_CLK
E17
OUT
LVTTL
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB2_D[3:0]
(CFG_D[3:0])
C17,D18,
D17,E18
IN
LVTTL
If CFG_CYC=0: Sideband Data Channel 2 Downstream Input
If CFG_CYC=1: Configuration data input
SB3_CLKI
J18
IN
LVTTL
Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is
registered at rising edge.
SB3_CLKO
H17
OUT
LVTTL
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB3_D[1:0]
G17,H18
IN
LVTTL
Sideband Data Channel 3 Downstream Input
SB4_CLKI
N17
IN
LVTTL
Sideband Data Channel 4 Downstream Asynchronous Clock Input. Data is
registered at rising edge.
SB4_CLKO
M18
OUT
LVTTL
Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB4_D[1:0]
K18,L18
IN
LVTTL
Sideband Data Channel 1 Downstream Input
Audio Interface
AI_C0
D2
IN
LVTTL
S/P-DIF Audio Channel 0
AI_C1
D1
IN
LVTTL
S/P-DIF Audio Channel 1
AI_C2
E1
IN
LVTTL
S/P-DIF Audio Channel 2
AI_C3
F1
IN
LVTTL
S/P-DIF Audio Channel 3
Other Signals
RESET#
A2
IN
LVTTL
Asynchronous Hardware Reset. Active LOW
ERROR
B2
OUT
LVTTL
Pixel Buffer Overrun
CFG_CYC
B1
OUT
LVTTL
Indicates that the configuration process is active
OSC
A3
IN
LVTTL
Reference Oscillator Input (see chapter 3.7)
CAP1
A15
IN
A
Loop filter pin Downlink 0
CAP2
B15
IN
A
Loop filter pin Downlink 0
CAP3
A8
IN
A
Loop filter pin Downlink 1
CAP4
B8
IN
A
Loop filter pin Downlink 1
NC
C1
–
–
Not connected
Table 4.7: INDT331B Transmitter Signals
* Configurable to LVTTL or Low Voltage Swing via VREF-pin
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