Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 28 of 40
Pin Name
Pin
Dir
Type
Description
Power Supply
VCC_CORE
C3,D3,E4,G7,G8,G10,H3,H8,J3,J4,J8,J11,L5,L6,L10,M3,M8,M11,
M12
IN
POWER
GND_CORE
D5,E5,E11,F4,F6,F11,G4,G6,H5,H6,H10,H12,J10,K3,K7,K8,K11,
L3,L11,M9
IN
GROUND
CMOS core supply
VCC_IO
C4,D4,E2,E3,G9,G11,H4,H7,H11,J7,J12,K5,K6,K9,K10,L9,L12,M4,
M7
IN
POWER
GND_IO
A3,C5,E12,F3,F5,F12,G3,G5,G12,H9,J5,J6,J9,K4,K12,L4,L7,L8,M5,
M6,M10
IN
GROUND
CMOS digital I/O
supply
VCC_CML
F7,F8
IN
POWER
GND_CML
F9,F10
IN
GROUND
CMOS chip-to-chip
interface supply
VCC_SX
B4
IN
POWER
GND_SX
B5
IN
GROUND
CMOS uplink I/O
supply
VCC_IA
E8,E10
IN
POWER
GND_IA
E7,E9
IN
GROUND
Bipolar Chip-to-chip
interface supply
VCC_A0
A7,A10,C6,C7,C10,D6,D12
IN
POWER
GND_A0
A8,A9,B7,B10,C8,C9,D11,E6
IN
GROUND
Bipolar downlink I/O
supply
VCC_A1
D9,D10
IN
POWER
GND_A1
D7,D8
IN
GROUND
Bipolar PLL supply
Table 4.2: INDT166B Transmitter Power Supply
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
PX_D47
K13
PX_D35
N11
PX_D23
N5
PX_D11
L2
PX_D46
L14
PX_D34
P10
PX_D22
P4
PX_D10
K1
PX_D45
L13
PX_D33
N10
PX_D21
N4
PX_D9
K2
PX_D44
M14
PX_D32
P9
PX_D20
P3
PX_D8
J1
PX_D43
M13
PX_D31
N9
PX_D19
N3
PX_D7
J2
PX_D42
N14
PX_D30
P8
PX_D18
P2
PX_D6
H1
PX_D41
N13
PX_D29
N8
PX_D17
P1
PX_D5
H2
PX_D40
P14
PX_D28
P7
PX_D16
N1
PX_D4
G1
PX_D39
P13
PX_D27
N7
PX_D15
N2
PX_D3
G2
PX_D38
P12
PX_D26
P6
PX_D14
M1
PX_D2
F1
PX_D37
N12
PX_D25
N6
PX_D13
M2
PX_D1
F2
PX_D36
P11
PX_D24
P5
PX_D12
L1
PX_D0
E1
Table 4.3: INDT166B Transmitter Pixel Data Pin Numbers
4.2 INDR166B Receiver Signal Description
Pin Name
Pin
Dir
Type
Description
Link Interface
RX0+
B8
IN
CML
RX0–
B9
IN
CML
Serial Data Input (Downlink 0)
TX2+
A5
OUT
CML
TX2–
A4
OUT
CML
Serial Data Output (Uplink)
LOCK0
B6
OUT
LVTTL
Lock Indicator. HIGH when PLL of Downlink is properly locked
SYNC0
B2
OUT
LVTTL
High, when the Downlink is frame synchronous
EQ
C5
IN
LVTTL
Selects the Downlink equalizer (LOW=OFF; HIGH=ON)
Pixel Interface
PX_CLK
J14
OUT
LVTTL
Pixel clock 24 – 161 MHz,
PX_CLK_IN
A3
IN
LVTTL
Pixel clock 24 – 161 MHz, de-jitter feedback
PX_CLK_OUT
H14
OUT
LVTTL
Pixel clock 24 – 161 MHz, de-jitter feedback
PX_D[47:0]
(see Table
4.6)
OUT
LVTTL
Configurable parallel pixel data interface
PX_HSYNC
G13
OUT
LVTTL
Pixel data framing – Horizontal sync pulse (active HIGH)
PX_VSYNC
H13
OUT
LVTTL
Pixel data framing – Vertical sync pulse (active HIGH)
PX_DE
J13
OUT
LVTTL
Pixel data framing – Data enable (active HIGH)
Sideband Interface
SB0_CLK
A13
OUT
LVTTL
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB0_D[3:0]
(CFG_D[3:0])
A11,B11,A
12,B12
IN
LVTTL
If CFG_CYC=0: Sideband Data Channel 0 Upstream Input
If CFG_CYC=1: Configuration data input
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