Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 27 of 40
4 Signals
4.1 INDT166B Transmitter Signal Description
Pin Name
Pin
Dir
Type
Description
Link Interface
TX0+
B8
OUT
CML
TX0–
B9
OUT
CML
Serial Data Output (Downlink)
RX2+
A5
IN
CML
RX2–
A4
IN
CML
Serial Data Input (Uplink)
LOCK0
B6
OUT
LVTTL
Lock Indicator. HIGH when PLL of Downlink is properly locked
SYNC2
B2
OUT
LVTTL
HIGH when the Uplink is frame synchronous
Pixel Interface
PX_CLK+
K14
IN
LVTTL*
Pixel clock 24 – 161 MHz, diff + or single-ended
PX_CLK–
J14
IN
LVTTL*
Pixel clock 24 – 161 MHz, diff – pull to GND in single ended mode
PX_D[47:0]
(see Table
4.3)
IN
LVTTL*
Configurable parallel pixel data interface
PX_HSYNC
J13
IN
LVTTL*
Pixel data framing – Horizontal sync pulse (active HIGH)
PX_VSYNC
H13
IN
LVTTL*
Pixel data framing – Vertical sync pulse (active HIGH)
PX_DE
H14
IN
LVTTL*
Pixel data framing – Data enable (active HIGH)
VREF
G13
IN
A
Configures the input level of the pixel interface
Sideband Interface
SB0_CLK
A13
OUT
LVTTL
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB0_D[3:0]
(CFG_SEL[3:0])
A11,B11,A
12,B12
OUT
LVTTL
If CFG_CYC=0: Sideband Data Channel 0 Upstream Output
If CFG_CYC=1: Configuration vector output
SB1_CLK
E14
OUT
LVTTL
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB1_D[1:0]
D14,D13
OUT
LVTTL
Sideband Data Channel 1 Upstream Output
SB2_CLK
C13
OUT
LVTTL
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB2_D[3:0]
(CFG_D[3:0])
A14,B14,B
13,C14
IN
LVTTL
If CFG_CYC=0: Sideband Data Channel 2 Downstream Input
If CFG_CYC=1: Configuration data input
SB3_CLKI
G14
IN
LVTTL
Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is
registered at rising edge.
SB3_CLKO
F13
OUT
LVTTL
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB3_D[1:0]
E13,F14
IN
LVTTL
Sideband Data Channel 3 Downstream Input
Audio Interface
AI_C0
C2
IN
LVTTL
S/P-DIF Audio Channel 0
AI_C1
C1
IN
LVTTL
S/P-DIF Audio Channel 1
AI_C2
D2
IN
LVTTL
S/P-DIF Audio Channel 2
AI_C3
D1
IN
LVTTL
S/P-DIF Audio Channel 3
Other Signals
RESET#
B3
IN
LVTTL
Asynchronous Hardware Reset (active LOW)
ERROR
A2
OUT
LVTTL
Pixel Buffer Overrun
CFG_CYC
A1
OUT
LVTTL
Indicates that the configuration process is active
OSC
A6
IN
LVTTL
Reference Oscillator Input (see chapter 3.7)
CAP1
C11
IN
A
Loop filter pin of Downlink
CAP2
C12
IN
A
Loop filter pin of Downlink
NC
B1
–
–
Not connected
Table 4.1: INDT166B Transmitter Signals
* Configurable to LVTTL or Low Voltage Swing via VREF-pin
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