Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 15 of 40
2.4 Interface Configuration Scheme
Note: The low-speed downstream sideband is automatically enabled, when high-speed downstream sideband OR audio is
enabled. INDT and INDR must be configured within the same group.
Interface
Vector
Name
Vector
Bits
Pixel Interface
Description
Group
1111
24-bit
24 bits of pixel(n) sampled at rising edge of PX_CLK+
0100
24-bit
24 bits of pixel(n) sampled at falling edge of PX_CLK+
0101
24-bit
24 bits of pixel(n) sampled at both edges of PX_CLK+
1001
48-bit
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
1010
48-bit
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
V1
0000
18-bit
18 bits of pixel(n) sampled at rising edge of PX_CLK+
0001
18-bit
18 bits of pixel(n) sampled at falling edge of PX_CLK+
0010
18-bit
18 bits of pixel(n) sampled at both edges of PX_CLK+
0110
36-bit
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
Pixel
Interface
cfg0
0111
36-bit
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
V2
0000
Disable high-speed downstream sideband data channel
SB3 and SB4
4
S1
11XX
Enable high-speed downstream sideband data channel
SB3 and SB4
4
1100
Clocking: Asynchronous mode at downstream sideband
data channels SB3 and SB4
4
1111
Clocking: Synchronous mode at downstream sideband
data channels SB3 and SB4
4
Sideband
Interface
Tx
cfg1
1110
Tx only
Clocking: Sampling mode at downstream sideband data
channels SB3 and SB4
4
S2
X100
Disable upstream sideband data
X111
Enable upstream sideband data
01XX
Disable Audio
Audio +
High Speed
Upstream
SB1
cfg2
11XX
Enable Audio
A
0000
Inom = x1.0, Ipre = x1.3, algorithm 1
0001
Inom = x1.0, Ipre = x1.3, algorithm 2
0010
Inom = x1.0, Ipre = x1.6, algorithm 1
0011
Inom = x1.0, Ipre = x1.6, algorithm 2
0100
Inom = x1.0, Ipre = x1.9, algorithm 1
0101
Inom = x1.0, Ipre = x1.9, algorithm 2
0110
Inom = x1.3, Ipre = x1.6, algorithm 1
0111
Inom = x1.3, Ipre = x1.6, algorithm 2
1000
Inom = x1.3, Ipre = x1.9, algorithm 1
1001
Inom = x1.3, Ipre = x1.9, algorithm 2
1010
Inom = x1.6, Ipre = x1.9, algorithm 1
1011
Inom = x1.6, Ipre = x1.9, algorithm 2
1100
Inom = Ipre = x1.9
1101
Inom = Ipre = x1.3
1110
Inom = Ipre = x1.0
Pre-
Emphasis
For
Serial
Upstream
Trans-
mission
cfg3
1111
Rx only
Inom = Ipre = x1.6
Note: others than the above mentioned vector bit combinations are not allowed
Table 2.3: Configuration of the Pixel Interface Mode
2.5 Error Handling and Reset
The chips provide an error detection signal (ERROR pin) indicating incorrect video timings. It is recommended to reset the
chip after the ERROR pin went high.
4 Sideband Data Channel 4 (SB4) only available with INDT/R330B
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