Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 29 of 40
Pin Name
Pin
Dir
Type
Description
SB1_CLKI
E13
IN
LVTTL
Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is
registered at rising edge.
SB1_CLKO
E14
OUT
LVTTL
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB1_D[1:0]
D14,D13
IN
LVTTL
Sideband Data Channel 1 Upstream Input
SB2_CLK
C13
OUT
LVTTL
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB2_D[3:0]
(CFG_SEL[3:0])
A14,B14,B
13,C14
OUT
LVTTL
If CFG_CYC=0: Sideband Data Channel 2 Downstream Output
If CFG_CYC=1: Configuration vector output
SB3_CLK
G14
OUT
LVTTL
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB3_D[1:0]
F14,F13
OUT
LVTTL
Sideband Data Channel 3 Downstream Output
Audio Interface
AI_C0
C2
OUT
LVTTL
S/P-DIF Audio Channel 0
AI_C1
C1
OUT
LVTTL
S/P-DIF Audio Channel 1
AI_C2
D2
OUT
LVTTL
S/P-DIF Audio Channel 2
AI_C3
D1
OUT
LVTTL
S/P-DIF Audio Channel 3
Other Signals
RESET#
B3
IN
LVTTL
Asynchronous Hardware Reset (active LOW)
ERROR
A2
OUT
LVTTL
Pixel Clock Recovery Error
CFG_CYC
A1
OUT
LVTTL
Indicates that the configuration process is active
OSC
A6
IN
LVTTL
Reference Oscillator Input (see chapter 3.7)
CAP1
C11
IN
A
Loop filter pin of Downlink
CAP2
C12
IN
A
Loop filter pin of Downlink
NC
B1
–
–
Not connected
Table 4.4: INDR166B Receiver Signals
Pin Name
Pin
Dir
Type
Description
Power Supply
VCC_CORE C3,E3,G8,G10,J3,J4,J7,J11,L5,L6,L10,M8,M11
IN
POWER
GND_CORE E4,E11,F4,F11,F12,G4,G6,H6,H10,J10,K8,K11,L3,L8,M9
IN
GROUND
CMOS core supply
VCC_IO
C4,D3,D4,E2,F2,G7,G9,G11,H3,H4,H7,H8,H11,J8,J12,K5,K6,K9,
K10,L9,L12,M3,M4,M7,M12
IN
POWER
GND_IO
D5,E5,E12,F3,F5,F6,G3,G5,G12,H5,H9,H12,J5,J6,J9,K3,K4,K7,
K12,L4,L7,L11,M5,M6,M10
IN
GROUND
CMOS digital I/O
supply
VCC_CML
F7,F8
IN
POWER
GND_CML
F9,F10
IN
GROUND
CMOS chip-to-chip
interface supply
VCC_SX
B4
IN
POWER
GND_SX
B5
IN
GROUND
CMOS uplink I/O
supply
VCC_IA
E8,E10
IN
POWER
GND_IA
E7,E9
IN
GROUND
Bipolar Chip-to-chip
interface supply
VCC_A0
A7,A10,C6,C7,C10,D6,D12
IN
POWER
GND_A0
A8,A9,B7,B10,C8,C9,D11,E6
IN
GROUND
Bipolar downlink I/O
supply
VCC_A1
D9,D10
IN
POWER
GND_A1
D7,D8
IN
GROUND
Bipolar PLL supply
Table 4.5: INDR166B Receiver Power Supply
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
PX_D47
K14
PX_D35
P11
PX_D23
P5
PX_D11
L1
PX_D46
K13
PX_D34
N11
PX_D22
N5
PX_D10
L2
PX_D45
L14
PX_D33
P10
PX_D21
P4
PX_D9
K1
PX_D44
L13
PX_D32
N10
PX_D20
N4
PX_D8
K2
PX_D43
M14
PX_D31
P9
PX_D19
P3
PX_D7
J1
PX_D42
M13
PX_D30
N9
PX_D18
N3
PX_D6
J2
PX_D41
N14
PX_D29
P8
PX_D17
P2
PX_D5
H1
PX_D40
N13
PX_D28
N8
PX_D16
P1
PX_D4
H2
PX_D39
P14
PX_D27
P7
PX_D15
N1
PX_D3
G1
PX_D38
P13
PX_D26
N7
PX_D14
N2
PX_D2
G2
PX_D37
P12
PX_D25
P6
PX_D13
M1
PX_D1
F1
PX_D36
N12
PX_D24
N6
PX_D12
M2
PX_D0
E1
Table 4.6: INDR166B Receiver Pixel Data Pin Numbers
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