34 / 40 page

Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 34 of 40
5 Pin Assignment
5.1 INDT166B Transmitter
12
3456
789
10
11
12
13
14
A
CFG_
CYC
ERROR
GND_
IO
RX2-
RX2+
OSC
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB0_
D3
SB0_
D1
SB0_
CLK
SB2_
D3
B
NC
SYNC2
RESET#
VCC_
SX
GND_
SX
LOCK0
GND_
A0
TX0+
TX0-
GND_
A0
SB0_
D2
SB0_
D0
SB2_
D1
SB2_
D2
C AI_C1 AI_C0
VCC_
CORE
VCC_
IO
GND_
IO
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
CAP1
CAP2
SB2_
CLK
SB2_
D0
D AI_C3 AI_C2
VCC_
CORE
VCC_
IO
GND_
CORE
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
GND_
A0
VCC_
A0
SB1_
D0
SB1_
D1
E PX_D0
VCC_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
CORE
GND_
IO
SB3_
D1
SB1_
CLK
F PX_D2 PX_D1
GND_
IO
GND_
CORE
GND_
IO
GND_
CORE
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
CORE
GND_
IO
SB3_
CLKO
SB3_
D0
G PX_D4 PX_D3
GND_
IO
GND_
CORE
GND_
IO
GND_
CORE
VCC_
CORE
VCC_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
GND_
IO
VREF
SB3_
CLKI
H PX_D6 PX_D5
VCC_
CORE
VCC_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
IO
GND_
CORE
PX_
VSYNC
PX_
DE
J PX_D8 PX_D7
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
CORE
VCC_
IO
PX_
HSYNC
PX_
CLK–
K PX_D10 PX_D9
GND_
CORE
GND_
IO
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
IO
PX_D47
PX_
CLK+
L PX_D12 PX_D11
GND_
CORE
GND_
IO
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
VCC_
IO
PX_D45 PX_D46
M PX_D14 PX_D13
VCC_
CORE
VCC_
IO
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
IO
VCC_
CORE
VCC_
CORE
PX_D43 PX_D44
N PX_D16 PX_D15 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D41 PX_D42
P PX_D17 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D39 PX_D40
Table 5.1: INDT166B GigaSTaR Digital Display Link Transmitter Pin Assignment (Top View)
= Pin A1 Identifier