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8.3.5 UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing

8.3.5.1

UTOPIA Level 2 Functional Timing

Figure 8-25 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2,

the ATM device places address ‘00h’ on the address bus (which is mapped to Port 1). PHY device '1' (Port 1)

indicates to the ATM device that it can accept cell data by asserting TDXA[1]. On clock edge 4, the ATM device

selects PHY device '1'. On clock edge 5, the ATM device starts a cell transfer to PHY device '1' by asserting

TEN,

placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell.

On clock edge 6, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA..

On clock edge 13, PHY device ‘2’ asserts TDXA[2] to indicate to the ATM device that it is ready to accept cell data.

On clock edge 15, PHY device '1’ indicates that it cannot accept the transfer of a complete cell by deasserting

TDXA[1]. On clock edge 16, the ATM device deselects PHY device '1' and selects PHY device '2' by deasserting

TEN and placing PHY device '2's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell

to PHY device '2' by asserting

TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the

transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place

additional bytes of the cell on TDATA.

Figure 8-25. UTOPIA Level 2 Transmit Cell Transfer Direct Mode

TADR

TEN

TDATA

TSOX

…

TCLK

P43

P44

P45

P46

P47

P48

P42

01h

00h

Transfer

Cell To:

PORT 1

PORT 2

TDXA[1]

TDXA[2]

TDXA[3]

TDXA[4]

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