DS3182 datasheet(97/389 Pages) MAXIM

97 / 389 page

DS3181/DS3182/DS3183/DS3184

97 of 38

10 FUNCTIONAL DESCRIPTION

10.1 Processor Bus Interface

10.1.1 8/16-Bit Bus Widths

The external processor bus can be sized for 8 or 16 bits using the WIDTH pin. When in 8-bit mode (WIDTH=0), the

address is composed of all the address bits including A[0], the lower 8 data lines D[7:0] are used and the upper 8

data lines D[15:8] are not used and never driven during a read cycle. When in 16-bit mode (WIDTH=1), the

address bus does not include A[0] (the LSB of the address bus is not routed to the chip) and all 16 data lines

D[15:0] are used. See Figure 8-40 and Figure 8-42 for functional timing diagrams.

10.1.2 Ready Signal (

RDY)

The

RDY signal allows the microprocessor to use the minimum bus cycle period for maximum efficiency. When

this signal goes low, the

RD or WR cycle can be terminated. See Figure 8-48 for functional timing diagrams.

NOTE: The

RDY signal will not go active if the user attempts to read or write unused ports or unused registers not

assigned to any design blocks. The

RDY signal will go active if the user writes or reads reserved registers or

unused registers within design blocks.

10.1.3 Byte Swap Modes

The processor interface can operate in byte swap mode when the data bus is configured for 16-bit operation. The

A[0]/BSWAP pin is used to determine whether byte swapping is enabled. This pin should be static and not change

while operating. When the A[0]/BSWAP pin is low the upper register bits REG[15:8] are mapped to the upper

external data bus lines D[15:8], and the lower register bits REG[7:0] are mapped to the lower external data bus

lines D[7:0]. When the A[0]/BSWAP pin is high the upper register bits REG[15:8] are mapped to the lower external

data bus lines D[7:0], and the lower register bits REG[7:0] are mapped to the upper external data bus lines D[15:8].

See Figure 8-44 and Figure 8-45 for functional timing diagrams.

10.1.4 Read-Write / Data Strobe Modes

The processor interface can operate in either read-write strobe mode or data strobe mode. When MODE=0 the

read-write strobe mode is enabled and a negative pulse on

RD performs a read cycle, and a negative pulse on WR

performs a write cycle. When MODE=1 the data strobe mode is enabled and a negative pulse on

DS when R/W is

high performs a read cycle, and a negative pulse on

DS when R/W is low performs a write cycle. The read-write

strobe mode is commonly called the “Intel” mode, and the data strobe mode is commonly called the “Motorola”

mode.

10.1.5 Clear on Read / Clear on Write Modes

The latched status register bits can be programmed to clear on a read access or clear on a write access. The

global control register bit GL.CR1.LSBCRE controls the mode that all of the latched registers are cleared. When

LSBCRE=0, the latched register bits will be cleared when the register is written to and the write data has the

read.

The clear on write mode expects the user to use the following protocol:

1. Read the latched status register

2. Write to the registers with the bits set that need to be cleared.

This protocol is useful when multiple uncoordinated software tasks access the same latched register. Each task

should only clear the bits with which it is concerned; the other tasks will clear the bits with which they are

concerned.

The clear on read mode is simpler since the bits that were read as being set will be cleared automatically. This

method will work well in a software system where multiple tasks do not read the same latched status register. The

DS3182 Datasheet(PDF) 97 Page - Maxim Integrated Products

DS3182 Datasheet(HTML) 97 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL