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DS3182 Datasheet(PDF) 48 Page - Maxim Integrated Products

Part # DS3182
Description  Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU
PDF  389 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS3182 Datasheet(HTML) 48 Page - Maxim Integrated Products

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9
PIN
TYPE
FUNCTION
TNEGn /
TOHMOn
O
Transmit Negative AMI / Line OH Mask
TNEGn: When the port line is configured for B3ZS, HDB3 or AMI mode and the
framer is not configured for one of the “-OHM” modes (see Table 10-32) and the
transmit line interface pins are enabled (PORT.CR2.TLEN), a high on this pin
indicates that a negative pulse should be transmitted on the line. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TLCLKn line clock output pins, but it can be referenced to
the TCLKOn, TCLKIn, RLCLKn or RCLKOn pins.
This output signal can be inverted.
o
DS3: 44.736 Mbps +20ppm
o
E3: 34.368 Mbps +20ppm
o
CC52: 52 Mbps +20ppm
TOHMOn: When the framer is configured for one of the “-OHM” modes (see Table
10-32) and the transmit line interface pins are enabled (PORT.CR2.TLEN), the
transmit overhead mask signal is output on this pin. This signal is a delayed version
of TOHMIn or ROHMIn when in local loopback (three clock period delay). This signal
will be high to indicate that the data on TDATn is not valid data and can be
overwritten by external logic to add an external frame signal. This signal will be low to
indicate that the data on TDATn is valid. The signal is updated on the positive clock
edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is
updated on the falling edge of the clock. The signal is typically referenced to the
TLCLKn line clock output pins, but it can be referenced to the TCLKOn, TCLKIn,
RLCLKn or RCLKOn pins.
This output signal can be inverted.
TXPn
Oa
Transmit Positive Analog
TXPn: This pin and the TXNn pin form a differential AMI output which is coupled to
the outbound 75
W coaxial cable through a 2:1 step-down transformer (Figure 1-1).
This output is enabled when the TX LIU is enabled and the output is enabled to be
driven. When it is not enabled, it is in a high impedance state.
o
DS3: 44.736 Mbps +20ppm
o
E3: 34.368 Mbps +20ppm
o
CC52: 52 Mbps +20ppm
TXNn
Oa
Transmit Negative Analog
TXNn: This pin and the TXPn pin form a differential AMI output which is coupled to
the outbound 75
W coaxial cable through a 2:1 step-down transformer (Figure 1-1).
This output is enabled when the TX LIU is enabled and the output is enabled to be
driven. When it is not enabled, it is in a high impedance state.
o
DS3: 44.736 Mbps +20ppm
o
E3: 34.368 Mbps +20ppm
o
CC52: 52 Mbps +20ppm
RXPn
Ia
Receive Positive analog
RXPn: This pin and the RXNn pin form a differential AMI input which is coupled to the
outbound 75
W coaxial cable through a 2:1 step-up transformer (Figure 1-1). This input
is used when the RX LIU is enabled and is ignored when the LIU is disabled.
o
DS3: 44.736 Mbps +20ppm
o
E3: 34.368 Mbps +20ppm
o
CC52: 52 Mbps +20ppm
RXNn
Ia
Receive Negative analog
RXNn: This pin and the RXPn pin form a differential AMI input which is coupled to the
outbound 75
W coaxial cable through a 2:1 step-up transformer (Figure 1-1). This input
is used when the LIU is enabled and is ignored when the LIU is disabled.
o
DS3: 44.736 Mbps +20ppm
o
E3: 34.368 Mbps +20ppm
o
CC52: 52 Mbps +20ppm



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