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8.3.5.2

UTOPIA Level 3 Functional Timing

Figure 8-30 shows a multiport transmit-interface multiple cell transfer to different PHY devices. PHY port '1', ‘3’, ‘4’

indicate to the ATM device that they can accept cell data by asserting the TDXA[n]. On clock edge 2, the ATM

device selects PHY port '1' by putting address ‘00h’ on the address bus. On clock edge 5, the ATM device starts a

cell transfer to PHY port '1' by asserting

TEN, placing the first byte of cell data on TDATA, and asserting TSOX to

indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts TSOX as it continues to

place additional bytes of the cell on TDATA. On clock edge 13, PHY port ‘2’ asserts TDXA[2] to indicate it is ready

to accept a cell. On clock edge 15, PHY port ‘1’ deasserts TDXA[1] to indicate to the ATM device that it does not

have the availability to receive another complete cell. On clock edge 16, the ATM device selects PHY port '2' by

deasserting

TEN and placing PHY port '2's address on TADR. On clock edge 17, the ATM device starts the transfer

of a cell to PHY port '2' by asserting

TEN, placing the first byte of cell data on TDATA, and asserting TSOX to

indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues

to place additional bytes of the cell on TDATA.

Figure 8-30. UTOPIA Level 3 Transmit Multiple Cell Transfer Direct Mode

TADR

TEN

TDATA

TSOX

…

TSCLK

P43

P44

P45

P46

P47

P48

P42

01h

00h

Transfer

Cell To:

PORT 1

PORT 2

TDXA[1]

TDXA[2]

TDXA[3]

TDXA[4]

Figure 8-31 shows a multiport transmit-interface multiple cell transfer to different PHY devices. On clock edge 1,

the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it can accept cell

data by asserting TPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device

starts a cell transfer to PHY port 'N' by asserting

TEN, placing the first byte of cell data on TDATA, and asserting

TSOX to indicate the transfer of the first byte of the cell. On clock edge 7, the ATM device deasserts TSOX as it

continues to place additional bytes of the cell on TDATA. On clock edge 11, the ATM device polls PHY port 'M'. On

clock edge 12, the ATM device polls PHY port 'N'. On clock edge 13, PHY port 'M' indicates that it can accept the

transfer of a complete cell. On clock edge 14, PHY port 'N' indicates that it cannot accept the transfer of a complete

cell. On clock edge 16, the ATM device deselects PHY port 'N' and selects PHY port 'M' by deasserting

TEN and

placing PHY port 'M's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY port

'M' by asserting

TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of

the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place additional

bytes of the cell on TDATA.

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