DS3182 datasheet(2/389 Pages) MAXIM

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DS3181/DS3182/DS3183/DS3184

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FEATURES (continued)

§ Direct and Clear-Channel Packet Mapping

§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or

G.832) Framer(s)

§ Ports Independently Configurable for DS3, E3

(Full or Subrate) or Arbitrary Framing Protocols

Up to 52Mbps

§ Programmable (Externally Controlled or

Internally Finite State Machine Controlled)

Subrate DS3/E3

§ Full-Featured DS3/E3/PLCP Alarm Generation

and Detection

§ Built-In HDLC Controllers with 256-Byte FIFOs

for Insertion/Extraction of DS3 PMDL, G.751 Sn

Bit, and G.832 NR/GC Bytes and PLCP NR/GC

Bytes

§ On-Chip BERTs for PRBS and Repetitive Pattern

Generation, Detection, and Analysis

§ Large Performance-Monitoring Counters for

Accumulation Intervals of at Least 1 Second

§ Flexible Overhead Insertion/Extraction Ports for

DS3, E3, and PLCP Framers

§ Loopbacks Include Line, Diagnostic, Framer,

Payload, Analog, and System Interface with

Capabilities to Insert AIS in the Directions Away

from Loopback Directions

§ Ports can be Disabled to Reduce Power

§ Integrated Clock Rate Adapter to Generate the

Remaining Internally Required 44.736MHz

(DS3), 34.368MHz (E3), and 52MHz (Arbitrary

Framing at Up to 52Mbps) from a Single Clock

Reference Source at One of Those Three

Frequencies

§ Pin Compatible with the DS3171/2/3/4 Family

and the DS3161/2/3/4 Family

§ 8/16-Bit Generic Microprocessor Interface

§ Low-Power (2.7W typ) 3.3V Operation (5V-

Tolerant I/O)

§ Small, High-Density, Thermally Enhanced, Chip-

Scale BGA Packaging (TE-CSBGA) with 1.27mm

Pin Pitch

§ Industrial Temperature Operation:

-40°C to +85°C

§ IEEE1149.1 JTAG Test Port

DETAILED DESCRIPTION

The DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs perform all the functions

necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3

(34.368Mbps) framed, or 52Mbps clear-channel data streams on DS3, E3, or STS-1 physical copper lines. Each

line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and

data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal or can be

bypassed for direct clock and data inputs. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The

transmitter LIU drives standard pulse-shape waveforms onto 75

W coaxial cable or can be bypassed for direct clock

and data outputs. The jitter attenuator can be placed in either transmit or receive data path when the LIU is

enabled. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission

and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in

properly formatted M23 DS3, C-bit DS3, G.751 E3, or G.832 E3 data streams. PLCP framers provide legacy ATM

transmission-convergence support. DSS scrambling is performed for clear-channel ATM cell support. With

integrated hardware support for both cells and packets, the DS318x DS3/E3 ATM/Packet PHYs provide system on-

chip solutions (from DS3/E3/STS-1 physical copper lines to ATM/Packet UTOPIA/POS-PHY Level 2/3 system

switch) for universal high-density line cards in the unchannelized DS3/E3/clear-channel DS3 ATM/Packet

applications. Unused functions can be powered down to reduce device power. The DS318x ATM/Packet PHYs with

embedded LIU conform to the telecommunications standards listed in Section 4.

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