DS3182 datasheet(95/389 Pages) MAXIM

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Considerations

Select the HDLC Controller connection. The default setting connects it to the DS3/E3 Framers.

Setting

PORT.CR1.HDSEL = 1 connects the HDLC Controller to the PLCP framers.

In POS-PHY mode, to select cell processing rather than packet processing, set PORT.CR2.PMCPE = 1.

For best performance of the CLAD to meet jitter requirements across the temperature range, especially @ -40 C,

the following test registers should be set after reset:

Address 0x20B = 0x11

Address 0x20F = 0x11

9.1 Monitoring and Debugging

To determine if the device is receiving a good signal and that the chip is correctly configured for its environment,

check the following status registers.

Receive Loss of Lock – PORT.SR.RLOL – The clock recovery circuit of the LIU was unable to recover the clock

from the incoming signal. This may indicate that the LIU’s master clock does not match the frequency of the

incoming signal. Verify that the CLAD is configured to match the clock input on the CLKA, CLKB, and CLKC pins

(DS3, E3, STS-1). See Table 10-11.

Loss of Signal – LINE.RSR.LOS – This indicates that the LIU is unable to recover the clock and data because there

is no signal on the line, or that the signal is attenuated beyond recovery.

Loss of Frame – T3.RSR1.LOF (or E3751.RSR1 or E3832.RSR1) – This indicates that the framer was unable to

synchronize to the incoming data. Verify that the FM bits have been correctly configured for the correct mode of

traffic (DS3, E3 G.751, E3 G.832)

Other helpful techniques diagnose a problem include using Line Loopback and Diagnostic Loopback. These

features help to isolate and identify the source of the problem. Line Loopback will loop the receive input to the

transmit output, eliminating the transmit side input from the equation. Diagnostic Loopback will loop the transmit

output before the LIU to the receive framer, eliminating the analog Receive LIU and the receive side analog

circuitry.

One other potential problem is the Line Encoding/Decoding. The device needs to be configured in the same mode

as the far end piece of equipment. If the far end piece of equipment is transmitting and receiving HDB3/B3ZS

encoded data, the DS318x also must be configured to do the same. This is controlled by the LINE.TCR.TZSD and

the LINE.RCR.RZSD bits.

9.1.1 Cell/Packet FIFO

Check the status registers of the FIFO block. Common indicators to check would be the Transmit Underflow,

Transmit Overflow, and Receive Overflow status bits. These status bits are located in the FIFO.TSRL Register and

the FIFO.RSRL Register.

A Transmit Underflow indicates that the transmit cell processor or packet processor has attempted a read while

the FIFO was empty.

A Transmit Overflow indicates that either a start of cell or a start of packet or a short packet was received when the

FIFO was full. Additionally, if additional packet data is received when the FIFO is already full, it will result in an

abort status for the current packet and the Transmit Overflow being declared.

A Receive Overflow occurs when cell data is received while the FIFO is full. In a packet system, the overflow will

be declared when a start of packet or a short packet is received or packet data is received when the FIFO is full

resulting in an abort status for the current packet and the Receive Overflow being declared.

9.1.2 Cell Processor

Monitoring the Loss of Cell Delineation in the Cell Processor is recommended to insure proper operation. The LCD

status bit is located in the CP.RSR Register and indicates when an Out of Cell Delineation persists for a

programmed number of cells (set in the CP.RLTC Register).

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