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DS3182 Datasheet(PDF) 42 Page - Maxim Integrated Products |
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DS3182 Datasheet(HTML) 42 Page - Maxim Integrated Products |
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42 / 389 page  DS3181/DS3182/DS3183/DS3184 42 of 38 9 8 PIN DESCRIPTIONS Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board-level ATPG patterns for isolation of interconnect failures. 8.1 Short Pin Descriptions Table 8-1. DS3184 Short Pin Descriptions n = 1,2,3,4 (port number). Ipu (input with pullup), Oz (output tri-stateable), (needs an external pullup or pulldown resistor to keep from floating), Oa (analog output), Ia (analog input), IO (bidirectional in/out). All unused input pins without pullup should be tied low. PIN NAME TYPE FUNCTION PORT 4 PORT 3 PORT 2 PORT 1 LINE IO TLCLKn O Transmit Line Clock Output V11 C11 Y8 A8 TPOSn / TDATn O Transmit Positive AMI / Data V14 C14 V4 C4 TNEGn / TOHMOn O Transmit Negative AMI / Line OH Mask W14 B14 U4 D4 TXPn Oa Transmit Positive Analog W6 B6 M2 J2 TXNn Oa Transmit Negative Analog Y6 A6 M1 J1 RLCLKn I Receive Clock Input Y12 A12 W8 B8 RXPn Ia Receive Positive Analog W5 B5 R2 F2 RXNn Ia Receive Negative Analog Y5 A5 R1 F1 RPOSn / RDATn I Positive AMI / Data W15 B15 Y3 A3 RNEGn / RLCVn / ROHMIn I Negative AMI / Line Code Violation / Line OH Mask Output Y15 A15 W3 B3 DS3/E3 OVERHEAD INTERFACE TOHn I Transmit Overhead U11 D11 U8 D8 TOHENn I Transmit Overhead Enable T14 E14 T5 E5 TOHCLKn O Transmit Overhead Clock T11 E11 V8 C8 TOHSOFn O Transmit Overhead Start Of Frame T12 E12 V7 C7 ROHn O Receive Overhead T10 E10 U10 D10 ROHCLKn O Receive Overhead Clock T13 E13 U5 D5 ROHSOFn O Receive Overhead Start Of Frame U14 D14 Y2 B2 DS3/E3 SERIAL DATA, PLCP AND FRACTIONAL DS3/E3 OVERHEAD INTERFACE TCLKIn I Transmit Line Clock Input Y14 A14 W4 B4 TSOFIn / TOHMIn I Transmit Start Of Frame Input / OH Mask Input U12 D12 W7 B7 TSERn/ TPOHn / TFOHn/ I Transmit Serial Data / PLCP Overhead / Fractional Overhead V13 C13 T6 E6 TPDENIn / TPOHENn / TFOHENIn I Transmit Payload Data Enable Input / PLCP Overhead Enable / Fractional OH Enable Input U13 D13 V5 C5 TCLKOn / TGCLKn / TPOHCLKn O Transmit Clock Output / Gapped Clock / PLCP Overhead Clock Y13 A13 U7 D7 TSOFOn / TDENn / TPOHSOFn / TFOHENOn O Transmit Framer Start Of Frame / Data Enable / PLCP Overhead Start Of Frame / Fractional OH Enable Output V12 C12 Y7 A7 TPDENOn O Transmit Payload Data Enable Output W10 B10 Y9 A9 TPDATn O Transmit Payload Data V10 C10 W9 B9 RPDENIn / RFOHENIn I Receive Payload Data Enable Input / Fractional Overhead Enable Input W13 B13 U6 D6 RPDATn I Receive Payload Data Y10 A10 V9 C9 RSERn / RPOHn O Receive Serial Data / PLCP Overhead W11 B11 T9 E9 |
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