DS3182 datasheet(84/389 Pages) MAXIM

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Figure 8-36. POS-PHY Level 2 Transmit Multiple Packet Transfer to Different PHY Ports

(polled status mode)

TCLK

TADR

TPXA

…

TEN

TSOX

TEOP

TERR

TDAT

Transfer

To PHY

…

P62

P63

P64

TSPA

Figure 8-37 shows a multidevice receive interface in packet transfer mode multiple packet transfer. On clock edge

2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS device that it has a block

of packet data or an end of packet ready for transfer by asserting RPXA. On clock edge 4, the POS device selects

PHY port 'N'. On clock edge 5, the POS device indicates to PHY port 'N' that it is ready to accept a block of packet

data by placing its address on RADR and asserting

REN. On clock edge 6, PHY port 'N' starts packet transfer by

asserting RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first

transfer of the packet. On clock edge 7, PHY port 'N' deasserts RSOX as it leaves RVAL asserted and continues to

place additional bytes of the packet on RDATA. On clock edge 14, PHY port 'N' places the last byte of the packet

on RDATA, and asserts REOP to indicate that this is the last transfer of the packet. On clock edge 15, PHY port 'N'

deasserts RVAL and REOP ending the packet transfer process. On clock edge 16, the POS device deasserts

REN

and selects PHY port 'P'. On clock edge 17, PHY port 'N' tri-states its RVAL, RDATA, RSOX, REOP, and RERR

outputs and the POS device indicates to PHY port 'P' that it is ready to accept a block of packet data by placing its

address on RADR and asserting

REN. On clock edge 18, PHY port 'P' starts packet transfer by asserting RVAL,

placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the

packet. On clock edge 19, PHY port 'P' deasserts RSOX as it leaves RVAL asserted and continues to place

additional bytes of the packet on RDATA. While this example shows a different PHY port ('P') being selected for the

next packet transfer, the timing is identical if the same PHY port ('N') is chosen for the next packet transfer.

DS3182 Datasheet(PDF) 84 Page - Maxim Integrated Products