DS3182 datasheet(9/389 Pages) MAXIM

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DS3181/DS3182/DS3183/DS3184

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Figure 8-38. POS-PHY Level 3 Transmit Multiple Packet Transfer In-Band Addressing.......................................... 86

Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing........................................... 87

Figure 8-40. 16-Bit Mode Write.................................................................................................................................. 88

Figure 8-41. 16-Bit Mode Read ................................................................................................................................. 88

Figure 8-42. 8-Bit Mode Write.................................................................................................................................... 89

Figure 8-43. 8-Bit Mode Read ................................................................................................................................... 89

Figure 8-44. 16-Bit Mode without Byte Swap ............................................................................................................ 90

Figure 8-45. 16-Bit Mode with Byte Swap ................................................................................................................. 90

Figure 8-46. Clear Status Latched Register on Read................................................................................................ 91

Figure 8-47. Clear Status Latched Register on Write................................................................................................ 91

Figure 8-48. RDY Signal Functional Timing Writes ................................................................................................... 92

Figure 8-49. RDY Signal Functional Timing Read..................................................................................................... 92

Figure 10-1. Interrupt Structure ................................................................................................................................. 99

Figure 10-2. Internal TX Clock................................................................................................................................. 102

Figure 10-3. Internal RX Clock ................................................................................................................................ 103

Figure 10-4. Example IO Pin Clock Muxing............................................................................................................. 107

Figure 10-5. Reset Sources..................................................................................................................................... 108

Figure 10-6. CLAD Block ......................................................................................................................................... 111

Figure 10-7. 8KREF Logic ....................................................................................................................................... 113

Figure 10-8. Performance Monitor Update Logic .................................................................................................... 116

Figure 10-9. Transmit Error Insert Logic.................................................................................................................. 117

Figure 10-10. Loopback Modes ............................................................................................................................... 118

Figure 10-11. ALB Mux ............................................................................................................................................ 118

Figure 10-12. AIS Signal Flow ................................................................................................................................. 121

Figure 10-13. DS3 C-Bit or DS3 M23 (with C-Bit Generation) Frame..................................................................... 129

Figure 10-14. DS3 PLCP Frame.............................................................................................................................. 130

Figure 10-15. DS3 M23 (with C-bits used as payload) Frame ................................................................................ 131

Figure 10-16. E3 G.751 Frame................................................................................................................................ 131

Figure 10-17. E3 PLCP Frame ................................................................................................................................ 132

Figure 10-18. Example E3 G.751 Internal Fractional Frame................................................................................... 132

Figure 10-19. E3 G.832 Frame................................................................................................................................ 133

Figure 10-20. System Interface Functional Diagram ............................................................................................... 135

Figure 10-21. Normal Packet Format in 32-Bit Mode .............................................................................................. 136

Figure 10-22. Normal Packet Format in 16-Bit Mode .............................................................................................. 136

Figure 10-23. Byte Reordered Packet Format in 32-Bit Mode ................................................................................ 136

Figure 10-24. Byte Reordered Packet Format in 16-Bit Mode ................................................................................ 137

Figure 10-25. ATM Cell/HDLC Packet Functional Diagram .................................................................................... 141

Figure 10-26. Receive DSS Scrambler Synchronization State Diagram................................................................. 145

Figure 10-27. Cell Delineation State Diagram ......................................................................................................... 146

Figure 10-28. HEC Error Monitoring State Diagram................................................................................................ 147

Figure 10-29. Cell Format for 53-Byte Cell With 32-Bit Data Bus ........................................................................... 147

Figure 10-30. Cell Format for 52-Byte Cell With 32-Bit Data Bus ........................................................................... 148

Figure 10-31. PLCP Framer Functional Diagram .................................................................................................... 153

Figure 10-32. DS3 PLCP Frame Format ................................................................................................................. 154

Figure 10-33. DS3 PLCP G1 Byte Format .............................................................................................................. 155

Figure 10-34. E3 PLCP Frame Format.................................................................................................................... 159

Figure 10-35. E3 PLCP G1 Byte Format ................................................................................................................. 159

Figure 10-36. Fractional Payload Controller Detailed Block Diagram ..................................................................... 163

Figure 10-37. Data Group Format ........................................................................................................................... 165

Figure 10-38. Frame Format.................................................................................................................................... 165

Figure 10-39. Framer Detailed Block Diagram ........................................................................................................ 166

Figure 10-40. DS3 Frame Format............................................................................................................................ 168

Figure 10-41. DS3 Subframe Framer State Diagram .............................................................................................. 169

Figure 10-42. DS3 Multiframe Framer State Diagram............................................................................................. 170

Figure 10-43. G.751 E3 Frame Format ................................................................................................................... 177

Figure 10-44. G.832 E3 Frame Format ................................................................................................................... 179

Figure 10-45. MA Byte Format ................................................................................................................................ 180

Figure 10-46. HDLC Controller Block Diagram ....................................................................................................... 185

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