DS3182 datasheet(49/389 Pages) MAXIM

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DS3181/DS3182/DS3183/DS3184

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TYPE

FUNCTION

RLCLKn

Receive Line Clock Input

RLCLKn: This clock is typically used for the reference clock for the RPOSn / RDATn,

RNEGn / RLCVn / ROHMIn signals but can also be used as the reference clock for

the RSERn, RSOFOn / RDENn / RFOHENOn, RFOHENIn, TOHMIn / TSOFIn,

TFOHn / TSERn, TFOHENIn, TSOFOn / TDENn / TFOHENOn, TPOSn / TDATn and

TNEGn / TOHMOn signals. This input is ignored when the LIU is enabled.

This input signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

CC52: 52 MHz +20 ppm

RPOSn /

RDATn

Receive Positive AMI / Data

RPOSn: When the port line is configured for B3ZS, HDB3 or AMI mode and the

framer is not configured for one of the “-OHM” modes and the LIU is disabled, a high

on this pin indicates that a positive pulse has been detected using an external LIU.

The signal is sampled on the positive clock edge of the referenced clock pin if the

clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock.

The signal is typically referenced to the RLCLKn line clock input pins, but it can be

referenced to the RCLKOn output pins.

This input signal can be inverted.

RDATn: When the port line interface is configured for UNI mode or the framer is

configured for one of the “-OHM” modes, the un-encoded receive signal is input on

this pin. The signal is sampled on the positive clock edge of the referenced clock pin if

the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the

clock. The signal is typically referenced to the RLCLKn line clock input pins, but it can

be referenced to the RCLKOn output pins.

This input signal can be inverted.

DS3: 44.736 Mbps +20ppm

E3: 34.368 Mbps +20ppm

CC52: 52 Mbps +20ppm

RNEGn /

RLCVn /

ROHMIn

Receive Negative AMI / Line Code Violation / Line OH Mask input

RNEGn: When the port line is configured for B3ZS, HDB3 or AMI mode and the

framer is not configured for one of the “-OHM” modes and the LIU is disabled, a high

on this pin indicates that a negative pulse has been detected using an external LIU.

The signal is sampled on the positive clock edge of the referenced clock pin if the

clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock.

The signal is typically referenced to the RLCLKn line clock input pins, but it can be

referenced to the RCLKOn output pins.

This input signal can be inverted.

DS3: 44.736 Mbps +20ppm

E3: 34.368 Mbps +20ppm

CC52: 52 Mbps +20ppm

RLCVn: When the port line interface is configured for UNI mode and the framer is not

configured for one of the “-OHM” modes, the BPV counter in the encoder/decoder

block is incremented each clock when this signal is high. The signal is sampled on the

positive clock edge of the referenced clock pin if the clock pin signal is not inverted,

otherwise it is sampled on the falling edge of the clock. The signal is typically

referenced to the RLCLKn line clock input pins, but it can be referenced to the

RCLKOn output pins.

This input signal can be inverted.

ROHMIn: When the port framer is configured for one of the “-OHM” modes, this signal

is used to mark the overhead bits on the RDATn pins when it is high. The DS318x

will ignore overhead bits. The signal is sampled on the positive clock edge of the

referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on

the falling edge of the clock. The signal is typically referenced to the RLCLKn line

clock input pins, but it can be referenced to the RCLKOn output pins.

This input signal can be inverted.

DS3182 Datasheet(PDF) 49 Page - Maxim Integrated Products

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