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DS3182 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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DS3182 Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 389 page  DS3181/DS3182/DS3183/DS3184 4 of 38 9 8.3.3 Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing ................. 72 8.3.4 Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing ....................................... 73 8.3.5 UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing........................................................... 75 8.3.6 Microprocessor Interface Functional Timing ........................................................................................ 88 8.3.7 JTAG Functional Timing....................................................................................................................... 92 9 INITIALIZATION AND CONFIGURATION 93 9.1 MONITORING AND DEBUGGING ....................................................................................................................... 95 9.1.1 Cell/Packet FIFO.................................................................................................................................. 95 9.1.2 Cell Processor...................................................................................................................................... 95 9.1.3 Packet Processor ................................................................................................................................. 96 10 FUNCTIONAL DESCRIPTION 97 10.1 PROCESSOR BUS INTERFACE......................................................................................................................... 97 10.1.1 8/16-Bit Bus Widths.............................................................................................................................. 97 10.1.2 Ready Signal ( RDY) ............................................................................................................................. 97 10.1.3 Byte Swap Modes ................................................................................................................................ 97 10.1.4 Read-Write / Data Strobe Modes......................................................................................................... 97 10.1.5 Clear on Read / Clear on Write Modes ................................................................................................ 97 10.1.6 Global Write Method ............................................................................................................................ 98 10.1.7 Interrupt and Pin Modes....................................................................................................................... 98 10.1.8 Interrupt Structure ................................................................................................................................ 98 10.2 CLOCKS ........................................................................................................................................................ 99 10.2.1 Line Clock Modes................................................................................................................................. 99 10.2.2 Sources of Clock Output Pin Signals ................................................................................................. 101 10.2.3 Line IO Pin Timing Source Selection ................................................................................................. 103 10.2.4 Clock Structures On Signal IO Pins ................................................................................................... 106 10.2.5 Gapped Clocks................................................................................................................................... 107 10.3 RESET AND POWER-DOWN .......................................................................................................................... 108 10.4 GLOBAL RESOURCES................................................................................................................................... 110 10.4.1 Clock Rate Adapter (CLAD)............................................................................................................... 110 10.4.2 8 kHz Reference Generation ............................................................................................................. 112 10.4.3 One Second Reference Generation................................................................................................... 114 10.4.4 General-Purpose IO Pins ................................................................................................................... 114 10.4.5 Performance Monitor Counter Update Details ................................................................................... 115 10.4.6 Transmit Manual Error Insertion ........................................................................................................ 116 10.5 PER-PORT RESOURCES............................................................................................................................... 117 10.5.1 Loopbacks.......................................................................................................................................... 117 10.5.2 Loss Of Signal Propagation ............................................................................................................... 119 10.5.3 AIS Logic ............................................................................................................................................ 119 10.5.4 Loop Timing Mode ............................................................................................................................. 122 10.5.5 HDLC Overhead Controller ................................................................................................................ 122 10.5.6 Trail Trace .......................................................................................................................................... 122 10.5.7 BERT.................................................................................................................................................. 122 10.5.8 Fractional Payload Controller............................................................................................................. 123 10.5.9 PLCP/Fractional port pins .................................................................................................................. 123 10.5.10 Framing Modes .................................................................................................................................. 127 10.5.11 Mapping Modes.................................................................................................................................. 129 10.5.12 Line Interface Modes.......................................................................................................................... 133 10.6 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE........................................................................................... 135 10.6.1 General Description ........................................................................................................................... 135 10.6.2 Features ............................................................................................................................................. 135 10.6.6 System Interface Bus Controller ........................................................................................................ 136 10.7 ATM CELL / HDLC PACKET PROCESSING.................................................................................................... 141 10.7.1 General Description ........................................................................................................................... 141 10.7.2 Features ............................................................................................................................................. 141 10.7.3 Transmit Cell/Packet Processor......................................................................................................... 142 10.7.4 Receive Cell/Packet Processor.......................................................................................................... 142 10.7.5 Cell Processor.................................................................................................................................... 143 |
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