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DS3182 Datasheet(PDF) 1 Page - Maxim Integrated Products |
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DS3182 Datasheet(HTML) 1 Page - Maxim Integrated Products |
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1 / 389 page  1 of 38 9 REV: 061604 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis. APPLICATIONS Access Concentrators SONET/SDH ADM Multiservice Access Platform (MSAP) SONET/SDH Muxes PBXs Multiservice Protocol Platform (MSPP) Digital Cross Connect Test Equipment ATM and Frame Relay Equipment Routers and Switches Integrated Access Device (IAD) PDH Multiplexer/ Demultiplexer ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS3181* 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3181N* -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3182* 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3182N* -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3183* 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3183N* -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3184 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3184N -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) *Future product—contact factory for availability. FUNCTIONAL DIAGRAM DS318x POS-PHY OR UTOPIA DS3/E3/STS-1 PORTS DS3/E3 FRAMER/ FORMATTER CELL/ PACKET PROCESSOR FEATURES § Single (DS3181), Dual (DS3182), Triple (DS3183), or Quad (DS3184) with Integrated LIU ATM/Packet PHYs for DS3, E3, and Clear- Channel 52Mbps (CC52) § Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform § Each Port Independently Configurable § Perform Receive Clock/Data Recovery and Transmit Waveshaping § Jitter Attenuator can be Placed Either in the Receive or Transmit Paths § Interfaces to 75W Coaxial Cable at Lengths Up to 380 Meters or 1246 Feet (DS3) or 440 Meters or 1443 Feet (E3) § Uses 1:2 Transformers on Both Tx and Rx § Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams § UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width § 66MHz UTOPIA L3 and POS-PHY L3 Clock § 52MHz UTOPIA L2 and POS-PHY L2 Clock § Ports Independently Configurable for Cell or Packet Traffic in POS-PHY Bus Modes § Direct, PLCP, DSS, and Clear-Channel Cell Mapping DS3181/DS3182/DS3183/DS3184 Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU www.maxim-ic.com POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc. |
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