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8.3.5.3

POS-PHY Level 2 Functional Timing

Figure 8-34 shows a multidevice transmit interface in byte transfer mode multiple packet transfer to different PHY

ports. Prior to clock edge 1, the POS device started a packet transfer to PHY port '1'. On clock edge 2, PHY port '1'

deasserts its TDXA to indicate to the POS device that it cannot accept any more data transfers. On clock edge 3,

the POS device stops the packet transfer to PHY port '1', and starts a packet transfer to PHY port '2' by leaving

TEN asserted, placing PHY port '2's address on TADR, placing the first byte of packet data on TDATA, and

asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 7, PHY port '2' deasserts its

TDXA to indicate to the POS device that it cannot accept any more data transfers. On clock edge 8, the POS

device stops the packet transfer to PHY port '2', and resumes a packet transfer to PHY port '3'. On clock edge 12,

PHY port '2' indicates to the POS device that it can accept a block of packet data by asserting its TDXA. Also, the

POS device indicates it is transferring the last byte of packet data by asserting TEOP. On clock edge 13, the POS

device ends the packet transfer to PHY port '3', and starts a packet transfer to PHY port '4'. On clock edge 15, PHY

port '1' indicates to the POS device that it can accept a block of packet data. On clock edge 17, PHY port '4'

deasserts its TDXA to indicate to the POS device that it cannot accept any more data transfers. On clock edge 18,

the POS device stops the packet transfer to PHY port '4', and resumes a packet transfer to PHY port '1'.

Figure 8-34. Transmit Multiple Packet Transfer to Different PHY ports (direct status

mode)

P36

P37

P38

'1'

TEN

TSOX

TEOP

TERR

TDATA

TCLK

TDXA[1]

TADR

TDXA[2]

TDXA[3]

TDXA[4]

Transfer

To Port

P34

P19

P20

P49

P63

…

'3'

P64

'4'

…

P50

'1'

P41

…

P42

P35

'2'

'1'

'2'

'3'

'4'

'1'

Figure 8-35 shows a multidevice receive interface in byte transfer mode multiple packet transfer from different PHY

ports/devices. Prior to clock edge 1, a packet data transfer was initiated from PHY port '1', and PHY ports '2', '3',

and '4' indicated to the POS device that they have a block of packet data or an end of packet ready for transfer by

asserting their RDXA. On clock edge 2, the POS device indicates to PHY port '1' that it cannot accept any more

data transfers by removing its address from RADR, and indicates to PHY port '2' that it is ready to accept a block of

packet data by placing its address on RADR and leaving

REN asserted. On clock edge 3, PHY port '1' stops

transferring packet data, and PHY port '2' starts a packet transfer by leaving RVAL asserted, placing the first byte

of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge

4, PHY port '2' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet

on RDATA. On clock edge 8, the POS device deasserts

REN to indicate to PHY port '2' that it cannot accept any

more data transfers. On clock edge 9, PHY port '2' ends the packet transfer process by deasserting RVAL and tri-

stating its RVAL, RDATA, RSOX, REOP, and RERR outputs. And, the POS device indicates to PHY port '3' that it

is ready to accept a block of packet data by placing its address on RADR and reasserting

REN. On clock edge 10,

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