TMPR4925 datasheet(369/590 Pages) TOSHIBA

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Chapter 11 Serial I/O Port

11-5

11.3.3

Serial Clock Generator

Generates the Serial Clock (SIOCLK). SIOCLK determines the serial transfer rate and has a

frequency that is 16

× the baud rate. One of the following can be selected as the source for the Serial

Clock (SIOCLK).

•

Internal System Clock (IMBUSCLKF)

•

External Clock Input (SCLK)

•

Baud rate generator circuit output

The IMBUSCLKF frequency can be selected from frequencies that are 1/5 the frequency of the CPU

clock. The maximum frequency tolerance of the external clock input (SCLK) is 45% the frequency of

IMBUSCLKF. For example, if IMBUSCLKF = 40 MHz, then set SCLK to 18 MHz or less.

The baud rate generator is a circuit that divides these clock signals according to the following

formula.

Baud Rate =

Divisor

Prescalar

•

fc: Clock frequency of IMBUSCLKF or an external clock input (SCLK)

•

Prescalar Value: 2, 8, 32, 128

•

Divide Value: 1, 2, 3,…255

Table 11.3.1 shows example settings of divide values relative to representative baud rates.

Figure 11.3.2 Baud Rate Generator and SIOCLK Generator

It is possible to correctly receive data if the error of the baud rate set by this controller is within 3.12

% of the target baud rate (communication baud rate).

Selector

Prescalar

Selector

SCLK

IMBUSCLKFF

Divider

Select CLK

SIBGR. BCLK

Baud Rate Generator

Select SIOCLK

SILCR. SCS [1]

SIOCLK

Baud Rate

Divide value

SIBGR. BRD

Select SIOCLK

SILCR. SCS [0]

1/2

1/8

1/32

1/128

1/1

− 1/255

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