TMPR4925 datasheet(121/590 Pages) TOSHIBA

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Chapter 7 External Bus Controller

7-11

7.3.6.3

Ready Mode

When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by

Ready input from an external device. Ready input is internally initialized. See Section “7.3.7.5

Ready Input Timing” for more information regarding the operation timing.

When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is

performed to see whether the Ready signal was asserted.

The Ready mode does not support Burst access by the internal bus.

Figure 7.3.3 Ready Mode

7.3.6.4

Page Mode

When in this mode, the ACK*/Ready pin becomes ACK* output when it is in the Dynamic

mode. When it is in the ACK*/Ready Static mode, the ACK*/Ready signal becomes High-Z.

Wait cycles are inserted into the access cycle according to the values of EBCCRn.PWT and

EBCCRn.WT. The Wait cycle count in the first access cycle of Single access or Burst access is

determined by the EBCCRn.WT value. The Wait cycle count can be set from 0 to 15. The Wait

cycle count of subsequent Burst cycles is determined by the EBCCRn.PWT value. The Wait cycle

count can be set from 0 to 3.

Figure 7.3.4 Page Mode

EBCCRn.PWT:WT=2

SYSCLK

CE*

ADDR [19:0]

OE*

DATA [31:0]

ACK*/READY

(Input)

Start Ready Check

EBCCRn.SHWT=0

SYSCLK

CE*

ADDR [19:0]

OE*

DATA [31:0]

ACK*/READY (Output)

EBCCRn.WT=2

EBCCRn.PWT=1

TMPR4925 Datasheet(PDF) 121 Page - Toshiba Semiconductor