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TMPR4925 Datasheet(PDF) 179 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 179 Page - Toshiba Semiconductor |
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179 / 590 page ![]() Chapter 8 DMA Controller 8-9 During Single Address transfer, the DMA Destination Address Register (DMDARn) and DMA Destination Address Increment Register (DMDAIRn) settings are ignored. Table 8.3.2 Channel Register Setting Restrictions During Single Address Transfer DMSARn[1:0] Transfer Setting Size (DMCCRn.XFSZ) DMSAIRn is “0” or greater DMSAIRn setting is a negative value DMSAIRn[1:0] DMCNTRn[1:0] 1 Byte ** ** ** ** 2 Bytes *0 *1 *0 *0 4 Bytes 00 11 00 00 4 Words 8 Words 16 Words 32 Words 00 11 4/0/-4 00 8.3.7.2 Burst Transfer During Single Address Transfer According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst transfer that spans across 32 word boundaries. Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size (DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that were specified by a Burst transfer. Therefore, the DMA Controller executes multiple Burst transactions of a transfer size smaller than the specified transfer size. This division method changes according to the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA Channel Control Register. Figure 8.3.2 shows the Single Address Burst transfer status when the lower 7 bits of the Transfer Start address are 0x54 and the transfer setting size (DMCCRn.XFSZ) is set to 4 words. Panel (a) of this figure shows the situation when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is “0”. In this case, first a three word transfer is performed up to the address aligned to the transfer setting size. Then, four word transfer specified by the transfer setting size is repeated. This setting is normally used. On the other hand, panel (b) shows when the Transfer Size Mode bit (DMCCRn.USEXFSWZ) is “1”. in this case, transfer is repeated according to the transfer setting size. Three word transfer and one word transfer is only performed consecutively without releasing bus ownership when transfer spans across a 32 word boundary. |
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