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TMPR4925 Datasheet(PDF) 190 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 190 Page - Toshiba Semiconductor |
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190 / 590 page ![]() Chapter 8 DMA Controller 8-20 8.3.15 Restrictions in Access to PCI Bus The PCI Controller detects a bus error if the DMA Controller performs one of the following accesses to the PCI Bus. • Burst transfer exceeding 8 words (PCICSTATUS.TLB) • Address Increment value –4 Burst transfer (PCICSTATUS.NIB) • Address Increment Value 0 Burst transfer (PCICSTATUS.ZIB) • Dual Address Burst transfer when the setting for DMSARn, DMDARn, or DMCNTRn is not a word boundary (PCICSTATUS.IAA) In addition, Single Address transfers between an external I/O device and the PCI Bus are not supported. Data transfer is not performed, but no error is detected. |
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