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TMPR4925 Datasheet(PDF) 193 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 193 Page - Toshiba Semiconductor |
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193 / 590 page  Chapter 8 DMA Controller 8-23 Bit Mnemonic Field Name Description 6:3 FIFUM[3:0] FIFO Use Enable [3:0] FIFO Use Enable [3:0] (Initial value: 0x0, R/W) Each channel specifies whether to use 8 -word FIFO in Dual Address transfer. FIFUM[n] corresponds to channel n. Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. 2 Reserved 1 RRPT Round Robin Priority Round Robin Priority (Initial value: 0, R/W) Specifies the method for determining priority among channels. 1: Round Robin method. Priority of the last channel used is the lowest, and the next previous channel has the next lowest priority. Round robin is in the order Channel 0 > Channel 1 > Channel > Channel 3. 0: Fixed Priority. Priority is fixed in the order Channel 0 > Channel 1 > Channel 2 > Channel 3. 0 MSTEN Master Enable Master Enable (Initial value: 0, R/W) This bit enables the DMA Controller. 1: Enable 0: Disable Note: If the entire DMA Controller is disabled, then all internal logic including the Bus Interface Logic and State Machine are reset. Figure 8.4.1 DMA Master Control Register (2/2) |
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