IMX8ULPIEC datasheet(3/100 Pages) NXP

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Table 1. i.MX 8ULP features (continued)

Feature type

Application processor domain Real-time processor domain

4x 32-bit timers

1x MQS

System timers

2x 12-bit ADC

2x DAC

2x analog CMP

8x DMIC (Dual/Stereo digital microphone

interface)

Low power audio video video domain

Processor

Tensilica HiFi4 DSP

Maximum Frequency up to 600 MHz

Quad MAC 32 with Dual Load/Store

Cached Based design with AXI access to LPDDR memory

Integrated Dual 2-way SMID VFPU

32-channel DMA

On-chip memory

64 KB on-chip RAM

32 KB instruction cache

64 KB data cache

64 KB ITCM

64KB DTCM

External memory interfaces

32-bit LPDDR3, LPDDR4, LPDDR4x

Graphics, display and Camera interface

GPU3D

• Support for Open GL ES 3.1, Vulkan 1.1, Open CL 2.x and Open VG1.1

GPU2D Composition Processing Core (CPC) GPU

4-lane MIPI DSI interface

Dual lane MIPI CSI interface

Image Sensing interface (ISI) with one pixel link interface

PXP E-Ink Display Engine

Display controller (DCNano) that supports EPDC panels through MIPI, Smart

Displays and Video mode

Can be optionally powered off when not in use

Audio peripherals

2 I2S ports

Timers

1x 32-bit Timer

Table continues on the next page...

NXP Semiconductors

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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