IMX8ULPIEC datasheet(73/100 Pages) NXP

Part #	IMX8ULPIEC

Description	i.MX 8ULP Applications Processor-Industrial Products

PDF	100 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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73 / 100 page

PDM_CLK

PDM_DATAn

trh

trs

tfh

tfs

Left

Data

Right

Data

Left

Data

Right

Data

High

Impedance

High

Impedance

High

Impedance

Figure 28. Input/Output TIming Requirements

6.2.4 EPDC timing specifications

The following table containg the EPDC timing specifications,

AXI bus clock domain: 316.8 MHz

PIX clock domain: 300 MHz

Table 53. EPDC timing specifications

Parameter

EPDC IO ports

Note

EPDC output skew

GDCLK

Minimize the output skew to be <1/4

EPDC internal pixel clock cycle.

GDSP

GDRL

SDCLK

SDCLKN

SDLE

SDOEZ

SDOED

SDOE

SDDO[*]

SDCE[*]

SDSHR

EPDC input skew

PWRSTAT

Minimize the input skew to be <1/4

EPDC AXI bus clock cycle.

PWRIRQ

EPDC output skew

BDR[*]

Minimize the output skew to be <1/4

EPDC AXI bus clock cycle.

PWRCTRL[*]

PWRWAKE

PWRCOM

NXP Semiconductors

Specifications—LPAV domain

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

73 / 100

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