IMX8ULPIEC datasheet(55/100 Pages) NXP

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Figure 11. SD3.0 High-Speed mode Timing

5.4.2.2 AC timing specification of eMMC DDR52 and SD DDR50 modes

The following table lists the timing characteristics of eMMC DDR52 mode and SD DDR50 mode, and the following figure depicts

the input and output timing diagram at uSDHC IO pins. Note that SDx_DATA signals are triggered and sampled on both edges

of the clock, and the SDx_CMD signal is triggered and sampled only on rising edge.

Table 34. AC timing specifications of eMMC DDR52 and SD DDR50 modes

Parameter

Symbols

Min.

Max.

Unit

Card Input Clock

SD1

Clock Frequency (eMMC5.1 DDR)

fPP

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

MHz

uSDHC Output / Card Inputs SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

3.0

6.4

uSDHC Input / Card Outputs SDx_DATAx (Reference to CLK)

SD3

uSDHC Input Setup Time

tISU

2.4

—

SD4

uSDHC Input Hold Time

tIH

1.2

—

NXP Semiconductors

Specifications—application domain

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

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