IMX8ULPIEC datasheet(74/100 Pages) NXP

74 / 100 page

7 Specifications—real-time domain

7.1 Real time domain (RTD) power modes

Table 54. RTD power modes

Power Mode

Min. Voltage at the

pin (V) VDD_DIG0

Max Frequency

(MHz) CM33/

Fusion DSP

Biasing Setting

Description

Active

Over Drive

1.05

216/200

AFBB enabled

All logic is

functional in this

mode.

Allows Dynamic

Voltage

Scaling(DVS)

Normal Drive

127/127

AFBB enabled

Under Drive

0.9

38.4/38.4

ARBB enabled

Sleep

0.9

RBB enabled

(optional)

Core in Wait-for-

Interrupt (WFI)

Core, bus,

peripheral clock

gating configurable

by software

Deep Sleep

0.65

RBB enabled

Core is in wait-

for-interrupt(WFI)

state

Core/System

clock gated

Some peripheral

optional functional

SRAM

contents retained

POWER DOWN

0.65

RBB enabled

Core/System/

peripherals power

gated

SRAM with

configurable

retention

Comparator, LP

timers optionally

functional

DEEP POWER DOWN

RTD domain

completely power

gated

Table continues on the next page...

NXP Semiconductors

Specifications—real-time domain

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

74 / 100

IMX8ULPIEC Datasheet(PDF) 74 Page - NXP Semiconductors

IMX8ULPIEC Datasheet(HTML) 74 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL