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IMX8ULPIEC Datasheet(PDF) 1 Page - NXP Semiconductors |
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IMX8ULPIEC Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 100 page  The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm® Cortex®-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications. The i.MX 8ULP processor provides a 32-bit LPDDR3/ LPDDR4/LPDDR4X memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, and displays. Additionally, there are 2 co-processors connected to the Cortex-M33 core: PowerQuad and Casper, accelerating DSP and cryptography functions, respectively. Table 1. i.MX 8ULP features Feature type Application processor domain Real-time processor domain ARM Processor Dual core Cortex®-A35 Cortex®-M33F Frequency: 800 MHz Nominal (RUN) frequency: 216 MHz 32 KB instruction and 32 KB data cache 32 KB instruction and 32 KB data cache Floating Point Unit (FPU) Floating Point Unit (FPU) 512 KB of L2 cache with Snoop Control Unit (SCU) Memory Protection Unit (MPU) NEON™ SIMD engine Co-processor interface for • PowerQuad hardware accelerator (Fixed and floating point +FFT) DSP functions • CASPER Crypto/FFT engine — Tensilica DSP Fusion F1 DSP processor Nominal frequency: 200 MHz 32 channel DMA 32 channel DMA On-chip memory 64 KB of RAM 768 KB of Shared Memory, zero wait state 192 KB of Boot ROM 96 KB of Boot ROM Table continues on the next page... MCIMX8xxxxxxxxx 485 MAPBGA 15 x 15 mm, 0.5 mm pitch IMX8ULPIEC i.MX 8ULP Applications Processor—Industrial Products Rev. 1 — 09/2023 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. |
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