IMX8ULPIEC datasheet(9/100 Pages) NXP

9 / 100 page

1 i.MX 8ULP modules list

The i.MX 8ULP applications processor contains a variety of digital and analog modules.

In the Domain column in this table:

• APD = Application Power or A35 Domain (primarily controlled by the Cortex-A35 core)

• RTD = Real-Time or M33 Domain (primarily controlled by the Cortex-M33 core)

• LPAVD/Flex = Low Power Audio Video domain

• DSPD: DSP Processor Domain

Module

Domain

Description

Memories and memory controllers

SRAM1

LPAVD

An AXI RAM Controller (RAMC), which acts as an interface between

the AXI bus and RAM, is used on each SRAM connected to the NIC

crossbar.

SSRAM

RTD

768KB of System Memory shared between M33, Fusion and other

Masters. SSRAM is divided into multiple partitions. System software

will determine how each partition is utilized and CPU/Master controlling

that partition. Fusion and M33 accesses these partition via dedicated

tightly couple memory buses (TCM), with zero wait-state. There is also

backdoor port that allows M33 DMA and other bus masters in the SoC

to access this memory.

XCACHE

RTD

The AHB Cache Controller (CAC) is a processor-local Level 1 (L1)

bus cache controller for use with cores using AMBA-AHB input/output

buses. It is optimized for minimum RunIDD (dynamic power).

LPDDR4C

APD, LPAVD

The LPDDR Controller is a configurable DDR controller that provides

interface to 32-bit LPDDR3, LPDDR4 and LPDDR4x memories. It

supports up to 2 GB DDR memory space. The LDDR4C includes

a DFI interface to work with PHY. The controller is responsible for

communication with the system through AXI interface, DDR commands

generation, DDR command optimizations, and read/ write data

path. The PHY performs timing adjustment using special calibration

mechanisms to ensure data capture margin at the supported clock

rate.

FlexSPI0-2

APD, RTD

The Flexible Serial Peripheral Interface (FlexSPI) module provides an

interface to various types of serial flash memory. The QSPI interface

allows up to two serial flash connections. It supports 1-bit, 4-bit and

8-bit SPI bus width.

uSDHC0-2

APD

The ultra Secure Digital Host Controller (uSDHC) provides the

interface between the host system and SD, SDIO or eMMC cards. The

uSDHC acts as a bridge, passing host bus transactions to the cards

by sending commands and performing data accesses to/from the cards

or devices. It handles SD, SDIO and eMMC protocol at transmission

level.

DMA, Bus Fabric and Gaskets

Table continues on the next page...

NXP Semiconductors

i.MX 8ULP modules list

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

9 / 100

IMX8ULPIEC Datasheet(PDF) 9 Page - NXP Semiconductors

IMX8ULPIEC Datasheet(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL