IMX8ULPIEC datasheet(60/100 Pages) NXP

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Table 39. MII transmit signal timing

Characteristic

Min.

Max.

Unit

ENET_TX_CLK to

ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

—

ENET_TX_CLK to

ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—

ENET_TX_CLK pulse width high

35%

65%

ENET_TX_CLK period

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

The following figure MII transmit signal timings, as described in the table.

ENET_TX_CLK (input)

ENET_TX_DATA3,2,1,0

ENET_TX_ER

ENET_TX_EN

(outputs)

Figure 18. MII transmit signal timing diagram

5.4.4.1.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)

The table below describes the timing parameter (M9) .

Table 40. MII asynchronous inputs signal timing

Characteristic

Min.

Max.

Unit

M91

ENET_CRS to

ENET_COL minimum

pulse width

1.5

—

ENET_TX_CLK period

1. ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

The following figure shows MII asynchronous input timings.

ENET_CRS, ENET_COL

Figure 19. MII async inputs timing diagram

NXP Semiconductors

Specifications—application domain

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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