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IMX8ULPIEC Datasheet(PDF) 49 Page - NXP Semiconductors |
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IMX8ULPIEC Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 100 page ![]() J14 J13 TCLK TRST Figure 8. TRST timing 4.7.2 SWD Electricals Table 28. SWD timing specificaions Symbol Description Min Max Unit J1 SWD_CLK frequency of operation — 25 MHz J2 SWD_CLK cycle period 1000/J1 — ns J3 SWD_CLK clock pulse width 20 — ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 37 ns J12 SWD_CLK high to SWD_DIO high-Z 2 — ns J2 J3 J3 J4 J4 SWD_CLK (input) Figure 9. Serial wire clock input timing NXP Semiconductors System specifications i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023 Data Sheet: Technical Data 49 / 100 |
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