IMX7DCEC datasheet(105/161 Pages) NXP

105 / 161 page

Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

105

4.10.8.9 Low-power receiver timing

Input Glitch Rejection of Low-Power Receivers

4.10.9 PCIe PHY parameters

The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the

PCI Express 1.1/2.0 standard.

4.10.9.1 PCIE_REXT reference resistor connection

The impedance calibration process requires connection of reference resistor 4.7 k 1% precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.10.10 Pulse width modulator (PWM) timing parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 70 depicts the timing of the PWM, and Table 78 lists the PWM timing parameters.

Figure 70. PWM Timing

Table 78. PWM output timing parameters

Parameter

Min

Max

Unit

PWM Module Clock Frequency

ipg_clk

MHz

2*TLPX

TMIN-RX

eSPIKE

Input

Output

VIH

VIL

IMX7DCEC Datasheet(PDF) 105 Page - NXP Semiconductors