IMX7DCEC datasheet(107/161 Pages) NXP

107 / 161 page

Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

107

NOTE

• For internal sampling, the timing values assumes using sample point 0,

that is QuadSPIx_SMPR[SDRSMP] = 0.

• For loopback DQS sampling, the data strobe is output to the DQS pad

together with the serial clock. The data strobe is looped back from DQS

pad and used to sample input data.

Figure 73. QuadSPI Output/Write Timing (SDR mode)

NOTE

Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default

value of 3 are shown on the timing. Please refer to the i.MX 6SoloX

Reference Manual (IMX6ULLRM) for more details.

Table 80. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)

Symbol

Parameter

Value

Unit

Min

Max

TIS

Setup time for incoming data

—

TIH

Hold time requirement for incoming data

—

Table 81. QuadSPI Output/Write Timing (SDR mode)

Symbol

Parameter

Value

Unit

Min

Max

TDVO

Output data valid time

—

2.5

TDHO

Output data hold time

-0.5

—

TCK

SCK clock period

—

TCSS

Chip select output setup time

—

SCK cycle(s)

TCSH

Chip select output hold time

—

SCK cycle(s)

TCSS

TCK

TCSH

TDVO

TDHO

TDVO

TDHO

QSPIx_SCLK

QSPIx_CS

QSPIx_SIO

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