LTM4673 datasheet(35/132 Pages) AD

35 / 132 page

LTM4683

Rev. 0

For more information www.analog.com

OPERATION

will occur. If the user does not wish to see the ALERT from

a PLL_FAULT, even if there is not a valid synchronization

signal at power-up, the ALERT mask for PLL_FAULT must

be written. See the description on SMBALERT_MASK for

more details. If the SYNC_nn pin is connected between

multiple ICs, only one of the ICs should have the SYNC_nn

pin enabled using the MFR_CONFIG_ALL[4] = 0, and all

other ICs should be configured to have the SYNC pin dis-

abled with MFR_CONFIG_ALL[4] = 1.

The ASEL_nn pin settings are described in Table 4.

ASEL_nn selects the subordinate address for the

LTM4683 internal controller. For more details, see Table 5.

NOTE: Per the PMBus specification, pin-programmed

parameters can be overridden by commands from the

digital interface, with the exception of ASEL_nn, which is

always honored. Do not set any part address to 0x5A or

0x5B because these are global addresses, and all parts

will respond to them.

Table 1. VOUTn_CFG Pin Strapping Look-Up Table for the

LTM4683’s Output Voltage, Coarse Setting (Not Applicable if

MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k

RVOUTn_CFG*

(kΩ)

VOUTn (V)

SETTING COARSE

MFR_PWM_

MODEn[1] BIT

Open

NVM

32.4

NVM

0.787

0.7

0.5

*RVOUTn_CFG value indicated is nominal. Select RVOUTn_CFG from a resistor

vendor such that its value is always within 3% of the value indicated in the table.

Consider resistor initial tolerance, T.C.R. and resistor operating temperatures,

soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal

shock/cycling, moisture (humidity), and other effects (depending on one’s

specific application) could also affect RVOUTn_CFG’s value over time. All such

effects must be considered in order for resistor pin strapping to yield the

expected result at every SVIN power-up and/or every execution of MFR_RESET

or RESTORE_USER_ALL, over the lifetime of one’s product. RTOP = 14.3k is

external to the part. Example:

RTOP

14.3k

RVOUTn_CFG

SGND_nn

VOUTn_CFG

VDD25_nn

Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the

LTM4683’s Output Voltage, Fine Adjustment Setting (Not

Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k

RVTRIMn_CFG*

(kΩ)

VTRIM (mV) FINE ADJUSTMENT TO VOUTn

SETTING WHEN RESPECTIVE

Open

32.4

22.6

86.625

18.0

74.25

15.4

61.875

12.7

49.5

10.7

37.125

9.09

24.75

7.68

12.375

6.34

–12.375

5.23

–24.75

4.22

–37.125

3.24

–49.5

2.43

–61.875

1.65

–74.25

0.787

–86.625

–99

*RVTRIMn_CFG value indicated is nominal. Select RVTRIMn_CFG from a

resistor vendor such that its value is always within 3% of the value

indicated in the table. Consider resistor initial tolerance, T.C.R. and resistor

operating temperatures, soldering heat/IR reflow, and endurance of the

resistor over its lifetime. Thermal shock/cycling, moisture (humidity), and

other effects (depending on one’s specific application) could also affect

RVTRIMn_CFG’s value over time. All such effects must be considered in

order for resistor pin strapping to yield the expected result at every SVIN_nn

power-up and/or every execution of MFR_RESET, or RESTORE_USER_ALL

over the lifetime of one’s product. RTOP = 14.3k is external to the part.

Example:

14.3k

RTRIM_CFG BOT

SGND_nn

VTRIMn_CFG

VDD25_nn

LTM4673 Datasheet(PDF) 35 Page - Analog Devices

LTM4673 Datasheet(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL