LTM4673 datasheet(90/132 Pages) AD

90 / 132 page

LTM4683

Rev. 0

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PMBus COMMAND DETAILS

BIT

MEANING

10010b

10011b

10100b

10101b

10110b

10111b

11000b

11001b

11010b

11011b

11100b

11101b

11110b

11111b

This command has one data byte.

MFR_PWM_CONFIG

The MFR_PWM_CONFIG command sets the switching frequency phase offset to the falling edge of the SYNC signal.

The part must be in the Off state to process this command. The RUN pins must be low, or the channels must be com-

manded off. If either channel is in the RUN state and this command is written, the command will be NACK’d and a

BUSY fault will be asserted.

BIT

MEANING

Reserved

[6:5]

00b

01b

10b

11b

Input current sense gain

2x gain. 0mV to 50mV range

4x gain. 0mV to 25mV range

8x gain. 0mV to 10mV range

Reserved

Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until

VIN > VIN_ON. The SHARE_CLK pin will be

pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_

CLK pin will not be pulled low when VIN < VIN_OFF except

for the initial application of VIN.

Reserved

BIT [2:0]

CHANNEL 0 (DEGREES)

CHANNEL 1 (DEGREES)

000b

180

001b

270

010b

240

011b

120

100b

120

240

101b

240

110b

120

300

LTM4673 Datasheet(PDF) 90 Page - Analog Devices

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