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LTM4673 Datasheet(PDF) 65 Page - Analog Devices

Part # LTM4673
Description  Low VOUT Quad 31.25A or Single 125A μModule Regulator with Digital Power System Management
PDF  132 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4673 Datasheet(HTML) 65 Page - Analog Devices

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LTM4683
65
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
final configuration can be quickly developed and stored
in the LTM4683 EEPROM. Figure 30 illustrates the appli-
cation schematic for powering, programming and com-
munication with one or more LTM4683s via the ADI I2C/
SMBus/PMBus adapter regardless of whether or not sys-
tem power is present. If system power is not present, the
dongle will power the LTM4683 through the VDD33_nn
supply pin. To initialize the part when VINnn is not applied,
and the VDD33_nn pin is powered, use global address 0x5B
command 0xBD data 0x2B followed by address 0x5B
command 0xBD data 0xC4. The LTM4683 can now com-
municate with the internal EEPROM and read the project
file. To write the updated project file to the NVM, issue a
STORE_USER_ALL command. When VIN is applied, an
MFR_RESET must be issued to allow the PWM POWER
to be enabled and valid ADCs to be read.
Because of the adapter’s limited current sourcing capabil-
ity, only the LTM4683s, their associated pull-up resistors,
and the I2C pull-up resistors should be powered from the
VDD33 3.3V supply. In addition, any device sharing the I2C
bus connections with the LTM4683 should not have body
diodes between the SDA/SCL pins and their respective
VDD node because this will interfere with bus communica-
tion without system power. If VIN is applied, the DC1613A
will not supply the power to the LTM4683s on the board.
It is recommended that the RUNn pins be held low or no
voltage configuration resistors inserted to avoid providing
power to the load until the part is fully configured.
The LTM4683 is fully isolated from the host PC’s ground
by the DC1613A. The 3.3V from the adapter and the
LTM4683 VDD33_nn pin must be driven to each LTM4683
internal controller with a separate PFET. If both VIN and
VBIAS are not on, the VDD33_nn pins can be in parallel
because the on-chip LDO is off. The controller’s 3.3V
current limit is 100mA, but typical VDD33_nn currents are
under 15mA. The VDD33_nn does back drive the INTVCC/
VBIAS pin. Normally, this is not an issue if VIN is open.
LTpowerPlay: AN INTERACTIVE GUI FOR
DIGITAL POWER
The LTpowerPlay (see Figure 31) is a powerful Windows-
based development environment that supports Analog
Devices, Inc's digital power system management ICs,
including the LTM4683. The software supports a vari-
ety of different tasks. LTpowerPlay can evaluate Analog
Devices, Inc's ICs by connecting to a demo board or the
user application. LTpowerPlay can also be used in an
offline mode (with no hardware present) to build mul-
tiple IC configuration files that can be saved and reloaded
later. LTpowerPlay provides unprecedented diagnostic and
debug features. It becomes a valuable diagnostic tool
during board bring-up to program or tweak the power
system or to diagnose power issues when bring up rails.
LTpowerPlay utilizes Analog Devices, Inc's USB-to-I2C/
SMBus/PMBus adapter to communicate with one of the
many potential targets, including the DC2924A, DC3082A
demo boards, or a customer target system. The software
also provides an automatic update feature to keep the
revisions current with the latest set of device drivers
and documentation.
A great deal of context-sensitive help is available with
LTpowerPlay, along with several tutorial demos.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTM4683 internal controllers have a one-deep buf-
fer to hold the last data written for each supported com-
mand before processing, as shown in Figure 32, write
command data processing. When the part receives a new
command from the bus, it copies the data into the write
command data buffer, indicates to the internal processor
that this command data needs to be fetched, and con-
verts the command to its internal format so that it can be
executed. Two distinct parallel blocks manage command
buffering and command processing (fetch, convert, and
execute) to ensure the last data written to any command
is never lost. Command data buffering handles incoming
PMBus writes by storing the command data in the write
command data buffer and marking these commands for
future processing. The internal processor runs in parallel
and handles the sometimes slower task of fetching, con-
verting and executing commands marked for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long



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