LTM4673 datasheet(56/132 Pages) AD

56 / 132 page

LTM4683

Rev. 0

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APPLICATIONS INFORMATION

start-up mode, forced continuous mode is the default

running mode).

If a channel is enabled for discontinuous-conduction mode

operation, the inductor current is not allowed to reverse.

The reverse current comparator, IREV, turns off the bottom

MOSFET (MBn) just before the inductor current reaches

zero, preventing it from reversing and going negative.

Thus, the controller can operate in discontinuous (pulse-

skipping) operation. In forced continuous mode operation,

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined solely by the voltage on the COMPn

pin. In this mode, the efficiency at light loads is lower than

in discontinuous mode operation. However, continuous

mode exhibits lower output ripple and less interference

with audio circuitry. Forced continuous mode may result

in a reverse inductor current, which can cause the input

supply to boost. The VIN_OV_FAULT_LIMIT can detect this

(if SVIN_nn is connected to VIN01 and/or VIN23) and turn off

the offending channel. However, this fault is based on an

ADC read and can nominally take up to 100ms to detect.

If there is a concern about the input supply boosting, keep

the part in discontinuous conduction operation.

SWITCHING FREQUENCY AND PHASE

The switching frequency of the LTM4683’s channels is

established by its analog phase-locked-loop (PLL) lock-

ing on to the clock present at the module’s SYNC_nn

pin. The clock waveform on the SYNC_nn pin can be

generated by the LTM4683’s internal circuitry when an

external pull-up resistor to 3.3V (e.g., VDD33) is pro-

vided, in combination with the LTM4683 control IC’s

FREQUENCY_SWITCH command being set to one of the

following supported values: 250kHz, 350kHz, 425kHz,

500kHz, 575kHz, 650kHz, 750kHz. In this configuration,

the module is called a “sync main” (using the factory-

default setting of MFR_CONFIG_ALL[4] = 0b), SYNC_nn

becomes a bidirectional open-drain pin, and the LTM4683

pulls SYNC logic low for nominally 500ns at a time, at the

prescribed clock rate. The SYNC signal can be bused to

other LTM4683 modules (configured as “sync subordi-

nates”) for purposes of synchronizing switching frequen-

cies of multiple modules within a system—but only one

LTM4683 internal controller should be configured as a

“sync main”; the other LTM4683(s) should be configured

as “sync subordinates”.

The most straightforward way is to set its FREQUENCY_

SWITCH command to 0x0000 and MFR_CONFIG_

ALL[4] = 1b. This can be easily implemented with resis-

tor pin-strap settings on the FSWPH_nn_CFG pin (see

Table 3). Using MFR_CONFIG_ALL[4] = 1b, the LTM4683s

SYNC pin becomes a high impedance input only—i.e.,

it does not drive SYNC low. The LTM4683 module syn-

chronizes its frequency to the clock applied to its SYNC

pin. The only shortcoming of this approach is that in the

absence of an externally applied clock, the switching fre-

quency of the module will default to the low end of its

frequency-synchronization capture range (~225kHz).

If fault-tolerance to the loss of an externally applied SYNC

clock is desired, the FREQUENCY_SWITCH command of

a “sync subordinate” can be left at the nominal target

switching frequency of the application and not 0x0000

However, it is still necessary to configure MFR_CONFIG_

ALL[4] = 1b. With this combination of configurations,

the LTM4683’s SYNC_nn pins become a high-impedance

input, and the module synchronizes its frequency to that

of the externally applied clock, provided that the frequency

of the externally applied clock exceeds ~½. of the target

frequency (FREQUENCY_SWITCH). If the SYNC clock is

absent, the module responds by operating at its target

frequency, indefinitely. If and when the SYNC clock is

restored, the module automatically phase-locks to the

SYNC clock as normal. The only shortcoming of this

approach is that the EEPROM must be configured per

above guidance; resistor pin-strapping options on the

FSWPH_nn_CFG pin alone cannot provide fault-tolerance

to the absence of the SYNC clock.

The FREQUENCY_SWITCH register can be altered via I2C

commands, but only when the switching action is dis-

engaged, i.e., the module’s outputs are turned off. The

FREQUENCY_SWITCH command takes on the value stored

in NVM at SVIN power-up, but is overridden according to

a resistor pin-strap applied between the FSWPH_nn_CFG

pin and SGND only if the module is configured to respect

resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b).

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